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ET4508/ED5532: Computer Systems Architecture. Lecturer: Dr. Karl Rinne. Contact. Dr. Karl Rinne Room:F2-021 (moving…) ER2-018 (from 21/02/2005 on) Extension: 2309 Email: karl.rinne@ul.ie Web: http://www.ul.ie/~rinne. Please note…. Please pre-arrange all meetings

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Et4508 ed5532 computer systems architecture l.jpg

ET4508/ED5532: Computer SystemsArchitecture

Lecturer: Dr. Karl Rinne


Contact l.jpg

Contact

  • Dr. Karl Rinne

    • Room:F2-021 (moving…)ER2-018 (from 21/02/2005 on)

    • Extension: 2309

    • Email:karl.rinne@ul.ie

    • Web:http://www.ul.ie/~rinne

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Please note l.jpg

Please note…

  • Please pre-arrange all meetings

    • email karl.rinne@ul.ie

  • Regularly check the web

    • visit http://www.ul.ie/~rinne

      • latest announcements

      • additional exercises

      • etc

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Please note4 l.jpg

Please note…

  • This is a lecture dealing mainly with computer architectures / computer hardware

    • pace is fast, material is interesting and demanding

    • we’ll look at software only sporadically - whenever necessary… (x86 assembler or C Code fragments)

  • Interactive lectures

    • if you have any question, interrupt anytime…

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Please note…

  • Exercises will be given

    • in the lecture notes

    • on the web

    • during class

  • Take the time to study & solve exercises!

  • Tutorials for weeks 8-12 will be arranged if required

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Please note…

  • Lab(s) will be arranged to give you hands-on PC hardware experience

  • Lab(s) will take place from week 6

  • Can be completed

  • Lab report including post-lab research

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Please note7 l.jpg

Please note…

  • Try to attend all lectures!

    • Lecture will deviate somewhat from lecture notes

    • (Exam-relevant) exercises will be given and discussed

  • Lecture notes

    • very comprehensive

    • available in print room shortly (availability will be announced)

  • Complete lecture material (notes, slides, labs, assignment, exam papers, etc) is available online (www.ul.ie/~rinne/et4508.htm)

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Please note

  • Course pre-requisites

    • Basics of digital systems, digital primitives

      • Boolean algebra, combinational and sequential logic, gates, FFs, truth tables, timing diagrams, etc.

    • Computer number systems

      • decimal, hexadecimal, binary

      • conversions, logical operations, arithmetics

    • Computer data formats

      • ascii, bcd

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Grading and Exam

  • Grading

    • Final Term Exam:80%

    • Lab + Post-lab research + report:20%

  • Lab report due end of week 8 (Fri, 11am)

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Spring 2005 Special Announcement

  • Student services requested a change of classroom (for the duration of the semester)

    • D1-050C2-062

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Aims of the course

  • See how processors have evolved

  • Become familiar with the Intel x86 Architecture, from 8086 to P4

  • Become familiar with the Hardware Elements of a PC

  • Understand the directions in which PCs may evolve

  • Obtain some hands-on PC hardware experience

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Quotes…

  • “DOS addresses only 1 MB of RAM because we cannot imagine any applications needing more.”Microsoft, 1980

  • “I don’t think it’s that significant”Tandy president John Roach on the IBM PC

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Questions l.jpg

Questions…

  • What exactly is a PC?

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Questions…

  • What exactly is a PC?

IBM PC 1981

Apple I 1976

Sinclair ZX80 1980

Apple Mac 1984

Atari 400 1979

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Questions…

  • Who invented the PC?

  • Who controls the PC standards today?

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Course Outline (1)

  • Review Microprocessor Fundamentals

    • MPU Register set and Internal Architecture

    • MPU buses

    • Memory Considerations

    • MPU interfacing: Interrupts and DMA

  • Intel x86 Architecture

    • CISC vs RISC

    • Memory and Computer Performance

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Course Outline (2)

  • PC Architecture: Processor, Memory, Buses, I/O, Relevance to BIOS

  • PCI, ISA, PC Card, PC 104 and other interface standards

  • Serial and parallel interfaces (legacy to status quo)

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Text Books

  • Upgrading and Repairing PCs, Scott Mueller. Que 2000. ISBN: 0-7897-2542-8

  • The Indispensable PC Hardware Book, Hans-Peter Messmer. Addison Wesley Longman 1997. ISBN 0-201-40399-4

  • Computer Systems Architecture, A Networking Approach. Addison Wesley 2000. ISBN 0-201-64859-8

  • Digital Fundamentals, Floyd (8086 Section)

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Other Good References

  • The Intel Microprocessors: 8086 … Pentium Pro Processor, Barry B Brey (5th Edition), Prentice Hall 1997

  • PC Support Handbook

  • Bigelow’s book on PC Maintenance

  • Microprocessor Architecures, Steve Heath

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Useful Web-sites

  • Intel Home: www.intel.com

  • Intel Processor page: http://developer.intel.com/design/processor/

  • Intel Processor Hall of Fame: http://www.intel.com/intel/museum/25anniv/hof/hof_main.htm

  • Intel Processor Specs: http://www.intel.com/intel/museum/25anniv/hof/tspecs.htm

  • The Intel Museum: http://intel.com/intel/intelis/museum/

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Useful Web Sites (2)

  • How Microprocessors Work: http://intel.com/education/mpuworks/index.htm

  • Intel Processor Quick Reference: http://www.intel.com/pressroom/kits/processors/quickref.htm

  • Intel Developer Home: http://developer.intel.com/

  • Intel Pentium II: http://developer.intel.com/design/PentiumII/

  • Intel Pentium III: http://developer.intel.com/design/PentiumIII/

  • Intel Pentium 4: http://developer.intel.com/design/pentium4/

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Useful Web Sites (3)

  • Intel Desktop Boards (Motherboards): http://developer.intel.com/design/motherbd/

  • PC Design Guide (Microsoft and Intel): http://www.pcdesguide.org/

  • AMD Home: www.amd.com

  • AMD Athlon: http://www.amd.com/products/cpg/athlon/index.html

  • PC Guide: http://www.pcguide.com/index.htm

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Useful web sites 4 l.jpg

Useful Web Sites (4)

  • Barry B Brey's personal web-site with some PC and microprocessor hints

  • http://users1.ee.net/brey/

  • Exercise look up Brey’s description of a Microprocessor at

  • http://members.ee.net/brey/l16.htm

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Evolution of intel 80x86 family l.jpg

Year

Processor

Clock

Bus Width

Addressable Memory

Virtual Mem

Transistors

Comments

1978

8086

5MHz -> 10MHz

16-bits

1MB

-

29000

First 8086 – used in IBM/PC clones

1979

8088

5MHz -> 8MHz

8-bits

1Mb

-

29000

Used in IBM/PC & PC/XT

1982

80286

6MHz -> 12.5MHz

16-bits

16Mb

1Gb

134000

Used in PC/AT

1985

80386DX

16MHz -> 33MHz

32-bits

4Gb

64Tb

275,000

32-bit CPU & ext bus

Evolution of Intel 80x86 Family

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Slide25 l.jpg

Year

Processor

Clock

Bus Width

Addressable Memory

Virtual Mem

Transistors

Comments

1989

80486DX

25MHz -> 50MHz

32-bits

4Gb

64Tb

1.2 million

L1 Cache on chip, also on-chip FPU.

486 derivatives still around in low-cost internet appliances

1993

Pentium

60MHz – 100MHz

64-bits

4Gb

64Tb

3.1 million

Superscalar architecture

1995

Pentium Pro

150MHz -> 200MHz

64-bits

4Gb

64Tb

5.5 million

Dynamic execution architecture drives high-performing processor, integrated L2 Cache

1997

Pentium II

200MHz -> 533MHz

64-bits

4Gb

64Tb

7.5 million

Dual independent bus, dynamic execution, Intel MMXTM technology

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Exercise l.jpg

Exercise

  • Visit the Intel Processor Hall of Fame http://www.intel.com/intel/museum/25anniv/hof/hof_main.htm

  • Visit the Pentium III and P4 Home pages and also the AMD K6-3D Now and Athlon pages

  • Identify the unique new feature(s) of each processor

  • Write out entries for Pentium III, P4, IA-64 and Athlon that could be included in the Hall of Fame at a future date.

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Review of mpu fundamentals l.jpg

Review Of MPU Fundamentals

  • For Simplicity look at a simple model of an MPU

    • 8-bit

    • 64K address space

    • Intel style interface

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Simplified block diagram of a microcomputer l.jpg

Simplified Block Diagram of a Microcomputer

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Diagram of a generic microprocessor l.jpg

Diagram of a Generic Microprocessor

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General registers l.jpg

General Registers

  • Small set of internal registers - temporary data storage

  • CU ensures that data from the correct register is presented to the ALU

  • CU ensures that data is written back to correct register

  • Accumulator usually holds ALU result

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Status or flags register example l.jpg

Status or Flags Register (Example)

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Program counter register l.jpg

Program Counter Register

  • Points to the next register to be executed

  • Called Instruction Pointer in Intel x86 Architecture

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Stack pointer l.jpg

Stack Pointer

  • STACK: Part of memory where program data can be stored by a simple PUSH operation

  • Restore data by a POP

  • Stack is in main memory and is defined by the program

  • Stack Pointer (SP) keeps track of the next location available on the Stack

  • Organised as a FILO Buffer

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Stack exercise l.jpg

Stack Exercise

  • At the start of the following sequence the Stack Pointer has the value C000h. The following code is executed

  • PUSHAL; Push 8 bit accumulator data

  • PUSHPSW; Push 8 bit flags register

  • What is the value of the SP at this point?

  • The following instructions are executed without any further stack activity in the meantimePOPPSW; Restore 8 bit flags register

  • POPAL; Restore 8 bit accumulator data

  • What is the value of the SP at this point? Note how the POP order is the reverse of the PUSH order.

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Simple microprocessor model l.jpg

Simple Microprocessor Model

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Fetch decode execute l.jpg

Fetch-Decode-Execute

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Fetch-Decode-Execute (Memory)

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Instruction Cycle Examples

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Memory map l.jpg

Memory Map

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Simple memory devices 8 k prom ram l.jpg

Simple Memory Devices (8K PROM & RAM)

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Memory Read and Write Cycles

  • Hardware Control lines used by the CPU to Control reads and Writes to Memory

  • Active low signal RD# asserted for a Read Cycle

  • Active Low signal WR# indicates a write

  • RD# and WR# signals supply timing information to memory device

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Read cycle l.jpg

Read Cycle

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Read Cycle Timing Diagram

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Write cycle l.jpg

Write Cycle

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Write cycle timing diagram l.jpg

Write Cycle Timing Diagram

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Input and Output Cycles

  • Intel Architecture processors have an I/O address space, separate from memory (Code and Data)

  • Allow I/O devices to be decoded separately from memory devices

  • Use IOR# and IOW# signals for Input & Output

  • Exercise: Draw Input & Output Cycles following the memory cycle examples

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I o instructions l.jpg

I/O Instructions

  • Separate I/O instructions cause the IOR# or IOW# signals to be asserted

    • MOV AL, (400Fh) ; instruction provides 16-bit address

    • IN AL, 2Ch ; instruction provides an 8-bit address

  • Some processors only support a single address space - I/O devices are decoded in the memory map

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Advantages of memory mapped i o l.jpg

Advantages of Memory Mapped I/O

  • I/O locations are read/written by normal instructions - no need for separate I/O instructions

    • Size of instruction set reduced

  • Memory manipulations can be performed directly on I/O locations

  • No need for IOR# and IOW# pins

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Advantages of separate i o mapping l.jpg

Advantages of Separate I/O Mapping

  • All locations in memory map are available for memory

    • No block removed for I/O

  • Smaller, faster instructions can be used for I/O

  • Less Hardware decoding for I/O

  • Easier to distinguish I/O accesses in assembly language

  • Which mapping system is preferable? Why?

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Processor with multiple memory devices l.jpg

Processor with multiple memory devices

How do you allow many memory devices to drive the same bus?

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Device Selection and Data Buses

  • A PC board may have many memory devices, all attached to the same data bus

  • When the processor reads data from the bus, it is essential that only one device drives data onto the bus

  • The other memories must be electrically disconnected from the bus while the selected device drives it

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Device selection and data buses 2 l.jpg

Device Selection and Data Buses (2)

  • Use Address Decoding to ensure only one device is selected at a time

  • Use Tristate buffers to disconnect unselected devices from the data bus

  • Unselected devices have their outputs placed in the HIGH IMPEDANCE STATE – it’s as if their outputs were switched off

  • All outputs, except those of the selected device should be in the High Impedance state

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Tristate buffers and transceivers l.jpg

TriState Buffers and Transceivers

  • Simplest buffers have an Input, an Output and an Enable Input

    • Enable signals may be active high or low

  • When Enable signal is active the output follows the input

  • When the Enable signal is inactive the output of the buffer is effectively disconnected from the circuit

  • When the output is in High Impedance other devices can drive the bus in question

  • Bidirectional buffers (transceivers) are essentially two back-to back buffers

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Tristate buffers and transceivers 2 l.jpg

TriState Buffers and Transceivers(2)

  • CPUs, RAMs and ROMs all have tristate-able buffers on their data buses

  • Microprocessors normally have tristate-able address and control buses as well

  • Discrete buffer devices and transceivers can drive more devices (loads) than RAMs and ROMS

  • 74AC244 and 74AC245 are typical buffers and transceivers

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Tristate buffer 1 8 74ac244 l.jpg

TriState Buffer (1/8 74AC244)

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Address decoding l.jpg

Address Decoding

How do you select just one memory device?

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Address decoding57 l.jpg

Address Decoding

  • Need external decoding hardware to ensure that only one device is accessed at any one time

  • Simple techniques enable the Chip Enable of just one device, based on the address bus contents

    • Implement this system, consisting of 4 x (16K x 8) memories:

    • ROM0 - 0000h - 3FFFh

    • ROM1 - 4000h - 7FFFh

    • RAM0 - 8000h - BFFFh

    • RAM1 - C000h - FFFFh

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Simple address decoding example l.jpg

Simple Address Decoding example

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Discrete address decoder l.jpg

Discrete Address Decoder

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74ac138 3 to 8 decoder l.jpg

74AC138: 3-to-8 Decoder

Logic Diagram

A

Select

Inputs

0

1

2

3

4

5

6

7

B

C

‘138

Outputs

E1

Enable

Inputs

E2

E3

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Example fairchild 74ac138 l.jpg

Example: Fairchild 74AC138

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Address decoder with 74ac138 l.jpg

Address Decoder With 74AC138

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Address decoder with 74ac13863 l.jpg

Address Decoder With 74AC138

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Cascading 138s for more complex decoding l.jpg

Cascading ‘138s for MoreComplex Decoding

  • 74138 generates a unique output for a given binary input

  • You can cascade ‘138s for more complex and precise decoding

  • Each stage has a propagation delay associated with it

    • May affect your timing budget

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Cascaded 74138s l.jpg

Cascaded 74138s

SEL0

A13

A14

A15

A

0

1

2

3

4

5

6

7

SEL1

B

C

‘138

SEL5

E1

E2

E3

A0

A1

A2

A

A

A0

A1

A2

SEL7

Logic

High

OUT A000

IN A000

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

B

B

OUT A001

IN A001

C

C

OUT A002

IN A002

‘138

‘138

OUT A003

IN A003

OUT A004

IN A004

E1

E1

OUT A005

IN A005

E2

E2

OUT A006

MEMR

IN A006

E3

E3

OUT A007

IN A007

Logic

High

Logic

High

MEMW

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Modern decoding l.jpg

Modern decoding

  • Decoding in Motherboards is often done using Custom devices or PLDs

  • Custom devices usually have 74138s as a Library part

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Slide67 l.jpg

Memory Access Timing

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Read cycle no wait l.jpg

Read Cycle (No Wait)

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Example st eprom 27c256 l.jpg

Example: ST EPROM 27C256

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Read cycle wait states l.jpg

Read Cycle (Wait States)

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Interrupts l.jpg

Interrupts

  • Used to Halt the normal flow of instructions

  • Exceptions can be due to Hardware or Software

  • Hardware Interrupts are asynchronous to the processor

  • Could be asserted by an external device requesting action, e.g. a port ready to transfer data

  • Interrupts can be globally masked by the processor’s Interrupt Enable Flag (IE or I)

  • IE is set by STI and reset by CLI (or equivalent)

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Maskable non maskable interrupts l.jpg

Maskable & Non Maskable Interrupts

  • Maskable interrupts can be enabled/disabled using a flag (usually in the flags register

  • Non Maskable Interrupts (NMI) are top priority interrupts that can’t be masked out

  • NMIs often used for Parity Errors, Power fails etc

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Nmi example l.jpg

NMI Example

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Interrupts74 l.jpg

Interrupts

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Direct memory access dma l.jpg

Direct Memory Access (DMA)

  • DMA techniques improve system performance

  • External devices can transfer data directly to or from memory under hardware control

  • Other methods (e.g. interrupts) use software to transfer data and are slower

  • DMA is used when very high data rates are required

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Code to move data from input to memory l.jpg

Code to Move Data From Input to Memory

READ_BYTE:INAL, DX[13]

MOV[BX], AL[2]

INCBX[2]

DECCL[2]

JNZREAD_BYTE[10]

This Code takes 29 clock cycles

At 20MHz:

fclk = 20MHz; Tclk = 1/fclk = 50ns; 29 x 50ns = 1450ns = 1.45us per byte

1/(1.45us/B) = 670KB/s (slow)

DMA could achieve 10MB/s at the same clock frequency

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Mpu dma controller l.jpg

MPU + DMA Controller

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Dma in from memory to i o l.jpg

DMA In From Memory to I/O

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Dma timing from memory to output transfer l.jpg

DMA Timing, from Memory to Output Transfer

DREQ

HOLD

HLDA

DACK

ADDRESS

IOW

MEMR

DATA

address n

address n+1

valid

valid

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Dma in from i o out to memory l.jpg

DMA In From I/O Out to Memory

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Dma timing from input to memory transfer l.jpg

DMA Timing, from Input to Memory Transfer

DREQ

HOLD

HLDA

DACK

ADDRESS

IOR

MEMW

DATA

address n

address n+1

valid

valid

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