MPC 555: Queued Serial Module. MPC 555 QSM. QSPI: Queued Serial Peripheral Interface: full duplex serial, synchronous interface. 160B of queue RAM. SCI1 & 2 : serial communication interfaces. QSM Block Diagram. QSM Configuration Register. QSM Interrupts. QSM Configuration Register.
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MPC 555: Queued Serial Module
QSPI: Queued Serial Peripheral Interface:
full duplex serial, synchronous interface. 160B
of queue RAM.
SCI1 & 2: serial communication interfaces
0000: 16 bits; 1000: 8 bits; 1001: 9 bits; ….; 1111: 15 bits
Only CPU can write
Multiple peripheral CS can be asserted
CONT: continue asserting CS after
QSPI RAM each entry: 1 word of transmit data, 1 word of receive data, 1B of command
CPU writes the command
queue of QSPI
CPU writes transmit data
and enables QSPI.
QSPI completes the transfer,
sets the completion flag SPIF
SPE bit in SPCR1 to enable the QSPI.
When done QSPI disables itself.
If HALT in SPCR3 on, then QSPI halts after each serial transfer and sets