Mpc 555 queued serial module
This presentation is the property of its rightful owner.
Sponsored Links
1 / 19

MPC 555: Queued Serial Module PowerPoint PPT Presentation


  • 73 Views
  • Uploaded on
  • Presentation posted in: General

MPC 555: Queued Serial Module. MPC 555 QSM. QSPI: Queued Serial Peripheral Interface: full duplex serial, synchronous interface. 160B of queue RAM. SCI1 & 2 : serial communication interfaces. QSM Block Diagram. QSM Configuration Register. QSM Interrupts. QSM Configuration Register.

Download Presentation

MPC 555: Queued Serial Module

An Image/Link below is provided (as is) to download presentation

Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author.While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server.


- - - - - - - - - - - - - - - - - - - - - - - - - - E N D - - - - - - - - - - - - - - - - - - - - - - - - - -

Presentation Transcript


Mpc 555 queued serial module

MPC 555: Queued Serial Module


Mpc 555 qsm

MPC 555 QSM

QSPI: Queued Serial Peripheral Interface:

full duplex serial, synchronous interface. 160B

of queue RAM.

SCI1 & 2: serial communication interfaces


Qsm block diagram

QSM Block Diagram


Qsm configuration register

QSM Configuration Register


Qsm interrupts

QSM Interrupts


Qsm configuration register1

QSM Configuration Register


Qsm interrupt registers

QSM Interrupt Registers


Queued serial peripheral interface

Queued Serial Peripheral Interface


Mpc 555 queued serial module

QSPI

  • 2 wire half duplex or 3-wire full duplex.

  • Many baud rates, clocking, and interrupt options.

  • Transfer chunks (serial) 8-16 bits.

  • 160B RAM stores data (in and out), and commands/control words.

  • CPU can queue up to 32 serial transfers in one interaction.

  • A pointer points to the data to be transferred. Normally incremented after each transfer.


Qspi contd

QSPI contd.

  • QSPI has its own 4 chip-select pins.

  • The queued transfer commands can be run in a loop in wrap-around mode.

  • A standard delay of 17 IMB cycles (0.8µs) between two transfer commands (chunks of serial transfer).


Qspi programming

QSPI Programming

0000: 16 bits; 1000: 8 bits; 1001: 9 bits; ….; 1111: 15 bits


Qspi programming1

QSPI Programming


Qspi programming2

QSPI Programming

  • SPSR: QSPI Status register, a 8-bit subfield of SPCR3.

  • Many other sources of interrupt --- each with its own status and interrupt enable bit.

  • HALTA: Halt ack.

  • MODF: mode fault flag.


Qspi ram

QSPI RAM

Only CPU can write

Right justified


Ram commands

RAM Commands

Multiple peripheral CS can be asserted

CONT: continue asserting CS after

transfer completed.


Qspi overall operation

QSPI Overall operation

QSPI RAM each entry: 1 word of transmit data, 1 word of receive data, 1B of command

CPU writes the command

queue of QSPI

CPU writes transmit data

and enables QSPI.

QSPI completes the transfer,

sets the completion flag SPIF

SPE bit in SPCR1 to enable the QSPI.

When done QSPI disables itself.

If HALT in SPCR3 on, then QSPI halts after each serial transfer and sets

HALTA.


Qspi interrupt sources

QSPI Interrupt sources

  • Three sources of interrupt (all on the same vector).

  • SPIF (finished).

  • MODF: Mode fault (inconsistent configuration).

  • HALTA: acknowledge HALT.


Qsm initialization

QSM Initialization


Qsm op

QSM Op


  • Login