Test 2 Fall 2007 Post Mortem

1. Test 2 Fall 2007Post Mortem CSCE 211 Digital Design • Topics • Sequential Circuits November 20, 2007

2. 1. Draw State Diagram • Draw the state diagram for a coke machine that takes quarters and dimes (no nickels) and has two buttons C and D to select either cokes or diet dr. peppers. Assume to encourage loss of weight the management has decided cokes are $.50 and diet dr. peppers are $.35. Assuming no change is given.

4. 1b. How many inputs are there? $.10, $.25, C (coke), D (dr. pepper) 1c. How many rows in the transition table would there be? 8 or 9 states  log2 #states = #bits to encode state = 3 or 4 #rows = 2 #Inputs + #BitsForState = 27 or 28 = 128 or 256 1d. How many inputs bits are necessary if you use an encoder? two

5. 2. State diagram  Transition Table State table • x d=1 s3 d=1 d=0 d=0 s0 s1 d=0 d=0 s2 d=1 d=1

6. Current state Next state Input • 2b. 2 flip-flops s0 s1 d=1 s3 d=1 d=0 d=0 s2 s0 s1 d=0 d=0 s2 d=1 d=1 s3

7. 3. Excitation Tables • Given the transition Table

8. 3. Excitation Tables • Excitation of X-Y flip-flop

9. 3c. Excitation for JK and D A race condition is when the outputs of a circuit feedback to the inputs and change the output which again feedback and change the output …

10. 4. Transition  excitation table using JK Flip-flop inputs Next state Current state Input

11. 4. Transition  excitation table using D Next state Input Current state Input

12. 4d. Finish design of A (using D flip-flop) • D(A,B,C,X) = B AB 00 01 11 10 CX AC’X’ 00 01 11 10 X C A A’BX A’BC AB’

13. 4d. Finish design of A (using JK flip-flop) • JA(A,B,C,X) = B AB 00 01 11 10 CX 00 01 11 10 BX X C A BC

14. 4d. Finish design of A (using JK flip-flop) • KA(A,B,C,X) = B AB 00 01 11 10 CX 00 01 11 10 BX X C A BC

15. (4 pts) Give VHDL for a 4x1 mux. • entity mux is   port(      S1, S0:  in   bit;      D3, D2, D1, D0: in bit; • Y: out bit); • end mux; • Architecture M_arch of mux is • begin • Y <= D0 and not S1 and not S0 • or D1 and not S1 and S0 • or D2 and S1 and not S0 • or D3 and S1 and S0; • end M_arch;

16. 5. VHDL • (2 pts) What keyword would appear in a structural specification and immediately distinguish it from a behavioral specification? • Portmap (…) • (4 pts) Assuming a 5 bit Carry look ahead unit, what is the VHDL for Gblock? • Architecture of CLU is CLUarch • begin • Gblock <= G4 or G3 and P4 or G2 and P3 and P4 or G1 and P2 and P3 and P4 or G0 and P1 and P2 and P3 and P4; • end of CLUarch;

17. 6a.Draw the logic diagram for an increment register.

18. 6b.Draw the logic diagram for an decrement register.

19. 6c. Combine

20. 7a. Draw a 1x4 demultiplexer • x

21. 4-bit CLU Figure from Lecture 8 slide??? • Partial Full Adder from Mano Gi = Xi and Yi Pi = Xi xor Yi = Xi and not Yi or not Xi and Yi Si = (Xi and not Yi and not C) or (not Xi and Yi and not C) or (not Xi and not Yi and C) or (Xi and Yi and C) This requires 7 “and” gates, and so is not implementable.

22. PLA for PFA: Gi, Pi and …from Xi, Yi, C Xi • Gi = Xi and Yi • Pi = Xi xor Yi = Xi and not Yi or not Xi and Yi Yi Gi Pi

23. PLA for PFA: Sumi from Xi, Yi, Ci Xi • Si = (Xi and not Yi and not C) or (not Xi and Yi and not C) • or (not Xi and not Yi and C) or (Xi and Yi and C) Yi Ci Sumi