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LCUK Meeting Oxford, 29/1/2004 Joel Goldstein for the LCFI Collaboration Bristol, Lancaster, Liverpool, Oxford, QMUL, RAL. LCFI Collaboration Status Report. R&D for a vertex detector at NLC or TESLA Physics Studies Algorithm development and implementation Detector optimisation

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LCUK Meeting

Oxford, 29/1/2004

Joel Goldstein

for the LCFI Collaboration

Bristol, Lancaster, Liverpool, Oxford, QMUL, RAL

LCFI CollaborationStatus Report


Lcfi research programme

R&D for a vertex detector at NLC or TESLA

Physics Studies

Algorithm development and implementation

Detector optimisation

Mechanical Development

Ultra low-mass ladders

FEA/physical models

Detector Development

Fast CCD technology (50 MHz for TESLA)

Custom CMOS readout chips

LCFI Research Programme


Lc vertex detector
LC Vertex Detector

  • 800 Mchannels of 2020 m pixels in 5 layers

  • Optimisation:

    • Inner radius (1.5 cm?)

    • Readout time (50 s?)

    • Ladder thickness (0.1% X0?)


Physics studies
Physics Studies

  • Implement flavour tagging algorithms in LC software

  • Quantify physics impact of different configurations

  • Preparing framework

  • Many different options

    • Short term: SGV

    • Long term: JAS3

  • ZVTOP (SLD)

  • Benchmarking starting


Mechanical options

Target of 0.1% X0 per layer

(100m silicon equivalent)

Unsupported Silicon

Longitudinal tensioning provides stiffness

No lateral stability

Not believed to be promising

Semi-supported Ultra-thin Silicon

Detector thinned to epitaxial layer (20m)

Silicon glued to low mass substrate for lateral stability

Beryllium has best specific stiffness

Composites, ceramics, foams...

Novel Structures

Mechanical Options


Mechanical studies of be si

FEA Simulations

PhysicalPrototyping

Laser survey system

Adhesive

0.2mm

Beryllium substrate (250 μm)

Mechanical Studies of Be-Si

Thinned CCD (  20 μm)

~160 μm ripples at -60°C

  • Good qualitative agreement


New approaches
New Approaches

  • Be-Si unstable when cooled due to CTE mismatch

  • Choose substrate with closer CTE match

    • 100 μm carbon fibre

    • ceramic foam

  • Micromechanical techniques....

Microstages

replace glue pillars

Sandwich

UV lithography on dummy


Column parallel ccd

Separate amplifier and readout for each column

N+1

Column Parallel CCD

Readout time = (N+1)/Fout

Column Parallel CCD


Prototype cp ccd
Prototype CP CCD

CPC1 produced by E2V

  • Two phase operation

  • Metal strapping for clock

  • 2 different gate shapes

  • 3 different types of output

  • 2 different implant levels

  • Clock with highest frequency at lowest voltage


Cpc1 results
CPC1 Results

  • Noise ~ 100 electrons

  • Minimum clock ~1.9 V

  • Maximum frequency ~ 10 MHz

    • inherent clock asymmetry


Cp readout asic
CP Readout ASIC

CPR1 designed by RAL ME Group

  • IBM 0.25 μm process

  • 250 parallel channels with 20μm pitch

  • Designed for 50 MHz

  • Data multiplexed out through 2 pads


Cpr1 testing
CPR1 Testing

Voltage injection into ADC

  • Flash ADCs tested

  • Voltage and charge amplifiers tested

  • Voltage gain ~40

  • Very sensitive to timing and bias values

  • Outstanding digital problems



Last tuesday success
Last Tuesday: Success!

4 channels with test signal

Single channel histogrammed over 200 frames

4 channels

wirebonded to CCD


Wirebonded results
Wirebonded Results

  • Noise ~130 electrons

  • Noise from preamps negligible

  • Direct connections will be tested next


Future plans

Bump Bonding

Currently underway with VTT

Expect assemblies in March/April

Test Programme

Radiation effects on fast CCDs (Liverpool/Lancaster)

High frequency clock propagation (Oxford)

Next Generation ASIC

Cluster finding logic

Design work almost finished

Waiting for CPR1 results and final review

Next Generation CCD

Design work starting in next few weeks

Detector scale device

Future Plans


Summary

LCFI is on schedule and making good progress

Physics tools ready for detector optimisation

Semi-supported option studied in detail

New mechanical ideas discussed

CCD+ASIC operation achieved

CP CCDs are viable technology for linear collider

Next generation will be full-scale prototype CCDs

Accelerator technology choice will determine path

Summary


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