Paul J. Boudreaux Consultant & Senior Scientist University Research Foundation

1. Thermal Limitations and Solutions for Microelectronic Systems Driven by the Economics of Moore’s Law Paul J. Boudreaux Consultant & Senior Scientist University Research Foundation Laboratory for Physical Sciences College Park, MD 20740 boudreau@eng.umd.eduTel:301-935-6547 April 4, 2005 UMBC Presentation

2. What does the future portend for high performance microelectronic systems for thermal & power distribution? 93W/cm2 40W/cm2 68W/cm2 Think the shuttle has a thermal management problem? Consider the next generation of high performance chips: >160 Watts/cm2

3. State-of-the-Art Thermosyphon in Commercial Work Stations • 100 Watt - 6 pipe finned tower • 30 cubic inches • 30 fins per stack • 100-150 ft3/min air flow required • Cools only 1 chip (1cm2 )

4. Modern Impediments to Chip Design • Thermal Limitations < 90 oC Qjc • Current Density: JAl < 4 x 105Amps/cm2 • Material Breakdown Potential, Emax= Vmax/dmin Emax (typical)= 1 Volt/10 nanometers = 100 x 106 V/m • Power Density < 250 Watts/cm2 • Random Soft Errors in Logic & Analog Circuits • Signals are a countable number of electrons ~ < 105 electrons • Thermal noise fluctuations • Quantum noise: particle decay, cosmic rays, radiation induced SEU

5. Consider a Mixed Analog/Digital/MEMs System’s In-Plane Thermal Gradients • dT/dt , DT and CTE are major problems • Analog voltages are temperature sensitive • In-situ stress/strain causes failure thru DT Potential Solutions: Heat spreaders with high K values attached to the chip can help alleviate lateral DT problems. Placing the system or components into a forced isothermal environment also reduces DT, dT/dt and CTE related problems. Severing the thermomechanical heat path reduces or eliminates shock and vibration from entering the system while reducing weight.

6. Shannon-von Neumann-Landauer (SNL) Switching Energy Per Bit* Ebit>ESNL= kBT ln2 = 0.017eV @300K Using the Uncertainty Relations for x & t, one calculates the max integration density of binary switches ~ 5 x 1013 devices/cm2, Power Dissipation per unit Area ~ 4 x 106 W/cm2 ! Moore’s Law We are at a Thermal Management Barrier (TMB) long before we get to the limits from Moore’s law or the semiconductor laws of physics! * ”Limits to Binary Logic Switch Scaling – A Gedanken Model”, Zhirnov, et al, Proc. of IEEE, Vol. 91, No. 11, Nov 2003, pp1934-1938.

7. Spray Cooling:One Possible Answer A Phase Change Methodology to Heat Removal that is Isothermal While Also Severing the Thermomechanical Heat Path

11. Phase Change: Spray Cooling System Can Meet These RequirementsBut It Requires An Active Cooling System Delivery and Return Tubes (Can be Part of Chassis Frame with Quick-Disconnects) Vapor Return Heat Rejection Heat Acquisition Cooled MCM or IC Package Fan Spray Cooling Cap Condenser/ Heat Exchanger Electronic Circuit Board Low power density, low DT heat rejection Liquid Out Pump Filter Heat can be acquired at high power density levels, enabling circuitry to be compacted to very small board areas, while heat is rejected remotely, where providing larger condenser (radiator) areas and airflow is not a problem. Compact Pump-Condenser Unit Typically Mounted at Rear of Enclosure or Externally

12. Isothermal Spray Cooling Directly Onto the Chip Surface Pressurized Liquid from Pump Enters Spray Manifold Spray Nozzles Create Fine Cooling Mist Impinging on IC Chips Vapor and Excess Spray Drawn Out Suction Tube for Return to Condenser Liquid Inlet 20-30 psi Typical Suction Outlet 1 atm (Not Pressurized) Typical MCM Substrate (Illustrated with Integral BGA Package) IC Die (Shown Flip-Chip Mounted with Underfill) Printed Circuit Board

13. 400 Watt Ceramic Package/ MCM with Spray Cooled Lid 400W MCM Spray Nozzle Array Vapor Out Fluid In Top View w/Underside of Lid Side View w/Lid Attached

14. Phase Change: Spray Cooling Attributes • Used for point-of-source cooling or system wide cooling • Demonstrated > 150 W/cm2heat extraction • Forces Isothermal surface conditions wherever phase change occurs • Severs thermomechanical heat path enabling vibration and shock isolation • Direct heat removal from the IC chip surface for minimum Qj • Conformable to surfaces, small liquid volumes required • Phase change fluids enable the choice of operating conditions over a large temperature range (77K-380K) • Active cooling requires a “dead man’s hand” system to remove trapped heat within the system when power fails • Capable of reliable zero-g operation, gives additional cosmic ray protection from SEU due to electrostatic charge buildup in spacecraft • Mechanical pump reliability can be 99.999999% with redundancy • Phase change fluids require chemical and mechanical filters for long term reliability; fluids must be chemically stable, environmentally friendly • Will not meet $0.10/Watt commercial costs in present form

15. Consider the Materials Used for the Thermal Conductivity Part of the Problem Assumptions: • Simple thermal conductivity model - P=dq/dt = K A DT/d • State-of-the-Art CMOS • Random logic • Max clock rate • 3D Interconnected layers Man-made polycrystalline diamond could passively meet this requirement for thermal conductivity, K > 13W/cm C. Note: KDiamond= 20 W/cm C @ 25C, and also, KDiamond= 100W/cm C @ 100 Kelvin

16. Polycrystalline Synthetic Diamond Courtesy of Norton Diamond Film Electro-Magnetic Arc Deposition of Synthetic Diamond

17. Visible &Thermal Images of Ceramic and Diamond MCMs Visible Light Diamond Substrate Image Still Air & Room Temperature Ceramic Substrate False Color IR Thermal Image @ 10 Watts per Chip

18. Cray Research J90 Supercomputer

20. MCM Version of a Cray J90

21. SGI/Cray Research J90 Supercomputer Rack Mounted Flight Test Version Monitor Cray Hard Drive J90 Cabinet Module Power Supply Aircraft Interface

22. All Computers Are Architecturally Two Dimensional The first two architecturaldimensions are used for the circuit layout. The third architectural dimension is used for heat transfer.

25. 25KW 3D Diamond Cube Design Stacked Diamond MCMs Form Cube Design Diamond MCM with Cu-Polyimide Interconnects Layers @ 625 Watts/MCM Moving the heat laterally through the diamond substrate to the edge fins can produce reliable operational conditions in this 3D prototype demonstration system* at 2.5KW. Four 3D MCM interconnected substrates make up this prototype system. Spray cooling (phase change) extracts the heat from the two edge fin areas. * “Thermal Analysis of Spray Cooled 3D Interconnected Diamond Substrate MCMs: Comparison With Experimental Measurements”, Boudreaux, et al, IEEE on-line Journal Transactactions on Device and Materials Reliability, December 2004, pp594-604.

26. Schematic of 3D Machine Photo of Sub-nanosecond Cycle Time Machine

27. Consider High Performance CMOS Operating at 1 Volt Bias • A 100 Watt chip requires 100 Amperes • Electromigration concerns limit current densities to < 105 A/cm2 • Power distribution with distributed power converters is only 40 to 60% efficient, generating even more waste heat

28. How to Handle the Power Distribution? • Why are power converters so inefficient? • High values of RDS-on (>20 miliOhms) for semiconductor switches • Transformer inefficiency – poor ferrite performance • Switching power converters use low frequency <150 KHz • Is there a better way? • Integrated converters on chip at 100-200MHz • New semiconductor switch design • Nanoparticle ferrites for laminar transformers on chip

29. New Silicon NMOS 200A@1.2V Switch Assembly Top view • Si NMOS via 2m MOSIS • 0.4 X 0.4 cm2 chip • Copper BCB Fine line Package Interconnect • 10 micron thick Cu • C4 Flip Chip Bonded • 20 mil Cu-Invar-Cu Source Contact Plane • 17 meter Gate length Side view Packaged Chip Chip

30. 400 Amperes @ 1.2 Volts CMOSR DS(on)=179 microOhms • 2 picosecond “Turn on” time • CMOS Gate length 17 Meters • Made with MOSIS technology • 93% efficient power converter Working prototype of switching power converter

31. Conclusions & Observations • Spray cooling has demonstrated the capability to handle power density > 150 W/cm2 • Polycrystalline diamond is an excellent CTE matched heat spreader for Silicon ICs • Power converters “on-chip” are possible with efficiencies > 90% • On-chip currents of 200 to 400 Amperes are reliable at 1 volt • Random errors are a significant problem: • Redundancy (voting) is often not a viable solution with limited power • New “random error hardened” logic designs are required • Analog designs are now limited by these random level signals

33. A Case Study in Thermal Management and Power Distribution For a 3D Interconnected High Performance Microelectronic System Paul J. Boudreaux Consultant & Senior Scientist University Research Foundation Laboratory for Physical Sciences College Park, MD 20740 boudreau@eng.umd.eduTel:301-935-6547

34. Laser Embedded Graphite Resistors in Diamond 1K Ohm @ 500 Watts “As Grown” Diamond cut with a laser showing dark “residue” around circumference Laser induced graphite resistors in a diamond substrate with metal interconnect* * Boudreaux, et al, “Laser Induced Graphite Resistors in Synthetic Diamond”, International Journal of Microelectronics & Electronic Packaging, 1996, Volume 19 , pp 169-177.

35. Low system overhead Isothermal environment Qj < 90 oC Die attach thermal impedance minimized 3D interconnections allowed Clock speeds > 4GHz Bias voltage ~ 1 Volt High thermal conductivity materials CTE matching materials High (>90%) efficiency power supplies Phase change heat removal Moving & Expelling Heat

36. WHY? The “best” switching supplies are limited by the switching device’s RDS-on impedance, typically 10 – 20 miliOhms. What if a switching transistor were made with a gate length of 50 meters instead of 2 – 3 microns? Then RDS-on would be < 20 microOhms! At a clock speed of 200 MHz instead of 100 kHz, the L-C-R components are fully embedded and Integrated into die

37. déjà vuThis is not the first time the industry has run into TMB • Vacuum tube – ENIAC’s MTBF =15min Solution: Change Technology to transistors • Bipolar semiconductors – TTL, ECL, LSI~100W/cm2 Solution: Change Technology to CMOS • CMOS – ULSI > 100 W/cm2 Solution: ? Today we are better situated with new materials and cooling technology to deal with the problem. NOTE: Even if CMOS is not used, the thermal problem remains, i.e. SNL data. 3D structures introduce a paradigm shift in thermal design because prior systems were architecturally two dimensional; the third dimension was the surface where the heat was extracted. In a true 3D environment, this third dimension is used by interconnects, power distribution and bonding. New thermal concepts will be required to extract heat from such 3D systems.