Lecture 12

1. Lecture 12 • Logistics • HW4 due today • Last lecture • Timing diagrams • Hazards • Today • Time/space trade offs: Parallel prefix trees • Adders • The conclusion of combinational logic!!!

2. The “WHY” slide • Timing/space trade offs • In real life, complex logic circuits you will work on will not have one minimum circuit. You will have to learn to understand what parameters to optimize your design on, and be able to come up with “trade offs” suitable for your application or customer’s needs. • Adders • Arithmetic logic units (ALUs) such as adders and multipliers perform most computer instructions. Therefore, it is critical to know how they works, how they scale, and how they may be optimized for time/space.

3. What do we mean by time/speed tradeoff?: Linear chains vs. trees • Lets say we want to implement an 8-input OR function with only 2-input gatesGates: 7Max delay: 7

4. Linear chains vs. trees • Now consider the tree version Gates: 7 Max delay: 3

5. And now we change the problem slightly • Build a circuit that takes 8 single bit inputs and calculates the OR of the first 2, the OR of the first 3, the OR of the first 4, and so on, up to the OR of all 8Gates: 7Max delay: 7

6. A parallel version of the prefix circuit Gates: 12Max delay: 3 0-6 0-7 0-5 0-3 0-1 0-2 0-4

7. The parallel prefix OR circuit Parallel Prefix n inputs n/2 OR gates per level log2n levels in-1 Parallel Prefix n/2 inputs on-1 in/2 on/2 on/2-1 in/2-1 Parallel Prefix n/2 inputs o0 i0

8. A B S Cout0 0 0 00 1 1 01 0 1 01 1 0 1 A Sum B Cout Half Adder Binary half adder • 1-bit half adder • Computes sum, carry-out • No carry-in • Sum = A'B + AB' = A xor B • Cout = AB

9. A B Cin S Cout0 0 0 0 00 0 1 1 00 1 0 1 00 1 1 0 11 0 0 1 01 0 1 0 11 1 0 0 11 1 1 1 1A B Cin S Cout0 0 0 0 00 0 1 1 00 1 0 1 00 1 1 0 11 0 0 1 01 0 1 0 11 1 0 0 11 1 1 1 1 A Sum Full Adder B Cout Cin Binary full adder • 1-bit full adder • Computes sum, carry-out • Carry-in allows cascaded adders • Sum = Cin xor A xor B • Cout = ACin + BCin + AB

10. Full adder: using 2 half adders A B Cin S CoutCout0 0 0 0 000 0 1 1 000 1 0 1 000 1 1 0 111 0 0 1 001 0 1 0 111 1 0 0 111 1 1 1 11 • Multilevel logic • Slower • Fewer gates • 2 XORs, 2 ANDs, 1 OR Sum = (A  B) Cin • Cout = ACin + BCin + AB • = (A  B)Cin + AB

11. 4-bit ripple-carry adder (also subtracts) • Easy to convert to subtractor using twos complement • Twos complement: A – B = A + (–B) = A + B' + 1 A2 B2 B2' A1 B1 B1' A0 B0 B0' B3' A3 B3 Sel Sel Sel Sel 0 1 0 1 0 1 0 1 B B B A A A A B 0  Add1  Subtract Cout Cin Cout Cin Cout Cin Cout Cin Sum Sum Sum Sum S3 S2 S1 S0 Overflow

12. Problem: Ripple-carry delay Carry propagation limits adder speed C0 S0 @2 A0 C1 @2 B0 S1 @3 A1 C2 @4 B1 S2 @5 A2 C3 @6 B2 A3 S3 @7 B3 Cout @8 111 0111 A + 0001 B -------------- ???? . @0 @0 1000 0000 @2N 0100 0110 @2N+1 Except when N=0 @0 @2N @2N+2 @0 @2N @0 @0 Cout takes two gate delays Cin arrives late

13. Cin S0 A0 B0 C1 S1 A1 B1 C2 S2 A2 B2 C3 S3 A3 B3 C4 C4 Can we be clever and speed this up? • Let’s compute all the carries in parallel • Derive carries from the data inputs • Not from intermediate carries • Use two-level logic • Compute all sums in parallel • How do we do that???

14. Speeding up the adder • Need to find a way to “predict” Cout for all bits • Without knowing what Cin is 0 + 0 -------- Predict Cout Cout is always 0 Call this PROPAGATE Cout is 0 if Cin is 0 Cout is 1 if Cin is 1 0 + 1 -------- Predict Cout • Let’s try all cases: • A = 0, B = 0 but not sure of Cin • A = 0, B = 1 but not sure of Cin • A = 1, B = 0 but not sure of Cin • A = 1, B = 1 but not sure of Cin Cout is 0 if Cin is 0 Cout is 1 if Cin is 1 1 + 0 -------- Predict Cout 1 + 1 -------- Predict Cout Call this GENERATE Cout is always 1

15. XOR XOR Ai Pi Si Bi 36 38 AND2 AND2 Ai Gi Bi 37 39 OR2 Ci Ci+1 40 Solution: Create a carry lookahead logicStep 1: Getting Pi an Gi Half Adder Half Adder A xor B xor Cin A xor B Sum Sum A Sum Cin(A xor B) AB Cout B Cout Cin Cout • Carry generate: Gi = AiBi • Generate carry when A = B = 1 • Carry propagate: Pi = Aixor Bi • Propagate carry-in to carry-out when (A xor B) = 1

16. Solution: Carry-lookahead logicStep 2: Calculate Sum and Cout • Sum and Cout in terms of generate/propagate: • Si = Ai xor Bi xor Ci = Pi xor Ci • Ci+1= AiBi + Ci(Ai xor Bi) = Gi + CiPi

17. Solution: Carry-lookahead logicStep 3: Express all carries in terms of C0 • Re-express the carry logic in terms of G and P C1 = G0 + P0C0 C2 = G1 + P1C1 = G1 + P1G0 + P1P0C0 C3 = G2 + P2C2 = G2 + P2G1 + P2P1G0 + P2P1P0C0 C4 = G3 + P3C3 = G3 + P3G2 + P3P2G1 + P3P2P1G0 + P3P2P1P0C0 • Implement each carry equation with two-level logic • Derive intermediate results directly from inputs • Rather than from carries • Allows "sum" computations to proceed in parallel

18. Ai Pi @ 1 gate delay Bi Si @ 2 gate delays Ci Gi @ 1 gate delay C0 C0 P0 P0 P1 P1 P2 P2 P3 G0 G0 P1 P2 P1 P2 C3 G1 P3 P2 G1 P2 P3 G2 C4 G2 P3 G3 Solution: carry-lookahead logicStep 4: implement with 2-level logic Logic complexity increases with adder size C0 P0 C1 G0 C0 P0 P1 G0 C2 P1 G1

19. Solution: Carry lookahead logic Get Pi (propagate) and Gi (generate) C0 S0 @2 A0 C1 @2 B0 S1 @3 A1 C2 @4 B1 S2 @5 A2 C3 @6 B2 A3 S3 @7 B3 C4@8 @0 Pi @1 @2 P0 G0 @3 @4 P1 G1 @3 @4 P2 G2 @3 C2 = G1 + P1C1 = G1 + P1G0 + P1P0C0 @4 Gi P3 G3 C3 = G2 + P2C2 = G2 + P2G1 + P2P1G0 + P2P1P0C0 C1 = G0 + P0C0 @3 C4 = G3 + P3C3 = G3 + P3G2 + P3P2G1 + P3P2P1G0 + P3P2P1P0C0

20. Cin S0 @2 A0 B0 C1 @3 S1 @4 A1 B1 C2 @3 S2 @4 A2 B2 C3 @3 S3 @4 A3 B3 C4 @3 C4 @3 Carry lookahead logic summary • Compute all the carries in parallel • Derive carries from the data inputs • Not from intermediate carries • Use two-level logic • Compute all sums in parallel • Cascade simple adders to make large adders • Speed improvement • Complex combinational logic

21. We've finished combinational logic... Negative numbers in binary Truth tables Basic logic gates Schematic diagrams Minterm and maxterm expansions (canonical, minimized) de Morgan's theorem AND/OR to NAND/NOR logic conversion K-maps, logic minimization, don't cares Multiplexers/demultiplexers PLAs/PALs ROMs Multi-level logics Timing diagrams Hazards Adders