Revolutionizing Design with Platform-Based Approach

1. Designing for 65nm and Beyond EDP 2005 Where’s The Revolution ?!? Greg Spirakis Absolutely, positively not working for Intel (or anyone else)

2. 48% 44% 1st Silicon Success 39% 33% Myth of Hard IP Reuse + Reliance on 20 Year Old Design Flow Failure 2002 1999 2004 Source*: Collett International Research and Synopsys The Move To SOC Designs Was A Failure

3. And It’s Going to Get Worse 1,000B 2007 2000 10B 2001 200 Simulation Vectors Engineer Years 100M 20 1995 1M 10M 100M Gates Source*: Synopsys 2,000 engineer years to write 25M lines of RTL and 1 Trillion simulation vectors to verify Closer Look

4. But Look Where We FocusDAC 2005 Session Summary • 47 Paper Sessions (plus 8 panels) • 9 Logic Design and Test • Error Tolerant Design • Programmable Architectures • SAT: Cool Algorithms and Hot Applications • Methods and Representations for Logic Synthesis • Advances in Synthesis • Advances in DFT Methods • Testing for Process and Timing Related Faults • New Directions in FPGA Technologies • CAD for FPGA • 5 ESL • Tools and Methods for the Verification of Processors and Processor-Based Systems • Matlab(TM) -The Other Emerging System-Design Language • Application Specific Architecture Design Tools • Formally Verifying Your 10-Million Gate Design • Effective Formal Verification Using Word-level Reasoning, Bit-level Generality, and Parallelism 75% Of Respins Due To Logic Problems But… 70% Of DAC Focused On Everything Else

5. Architecture Performance Model The Formal Equivalence/ Synthesis Void Abstraction limited by logic equivalence capabilities Less details allowing more designed functionality Layout/Schematic netlist compare Design rule checking What’s Wrong ? Highest Abstraction Level Product family manuals & docs Ultimately, “what” you want Architectural Family We need a dramatic increase in design abstraction while maintaining the link to the physical implementation Need a new design paradigm to further raise the level of abstraction!!! Abstract of “what” you will build Synthesizable RTL Abstracts of “how” you built it Structured RTL Formal Logic Equivalence Library gates Schematic gates Schematic transistors Layout polygons Transistor physics Lowest Abstraction Level

6. The Revolution Structured methodology that limits the space of exploration, yet achieves good results in the fixed time constraints of the design; A formal mechanism for identifying the most critical hand-off points in the design chain; A method for design re-use at all abstraction levels based on assembling and configuring platform components in a rapid and reliable fashion; An intellectual framework for the complete electronic design process. Platform Based Design Integrated Design and Verification • Raise the level of abstraction by creating a high level model (HLM) • Successively refine the design ensuring that each refinement is equivalent to the previous one • Tightly integrate logic and physical design domains • Enable extensive use of a repository of trusted design transformations generated during the design process A. Sangiovanni-Vincentelli, DAC June 04 G. Spirakis, DATE Feb 04

7. Platform: An abstraction layer in the design flow that facilitates a number of possible refinements into a subsequent abstraction layer (platform) in the design flow. Platform Stack: Every pair of platforms, the tools and methods that are used to map the upper layer of abstraction into the lower level one. Platform-based Designhttp://www.gigascale.org/pubs/141/platformv7eetimes.pdf Top-Down: • Define a set of abstraction layers • From specifications at a given level, select a solution (controls, components) in terms of components (Platforms) of the following layer and propagate constraints Bottom-Up: • Platform components (e.g., micro-controller, RTOS, communication primitives) at a given level are abstracted to a higher level by their functionality and a set of parameters that help guiding the solution selection process. The selection process is equivalent to a covering problem if a common semantic domain is used. A. Sangiovanni-Vincentelli

8. Integrated Design & Verification Ensure Final Implementation Maintains Equivalence To HLM While Meeting Design Goals Integrated Design and Verification • Raise the level of abstraction by creating a high level model (HLM) • Successively refine the design ensuring that each refinement is equivalent to the previous one • Tightly integrate logic and physical design domains • Enable extensive use of a repository of trusted design transformations generated during the design process

9. ValidationTarget f L L L L L L fa fb L L L L L L HLM Code Verify transformation is correct Use cross domain visibility between HLM and schematic Equiv An Example A higher level expressive language • Visualize the code • Ungroup/group, move logic to make simple optimizations

10. ValidationTarget HLM Code f L L L L L L Equiv fa fb L L L L L L • Visualize the code • Ungroup/group, move logic to make simple optimizations Equiv • Refine the design • Replace some blocks with circuits from lib • Create new circuits and replace blocks • Synthesize other blocks • Apply trusted transformations • Determine feasibility L L L L L L fc fd fe ff An ExampleSuccessive Refinement

11. ValidationTarget HLM Code Equiv Final Netlist equivalent to HLM !!! f L L L L L L • Visualize the code • Ungroup/group, move logic to make simple optimizations fa fb L L L L L L Equiv • Refine the design • Replace some blks with circuits from lib • Create new circuits and replace blocks • Synthesize other blocks • Apply trusted transformations • Determine feasibility L L L L L L fc fd fe ff Equiv L L L L L L fg fh fi fj fk fl Today’s Netlist An ExampleFurther Design Refinement Many Iterations • Iteratively, further refine the design • Replace some blocks with circuits from lib • Create new circuits and replace blocks • Synthesize other blocks • Apply trusted transformations • Determine feasibility

12. Analyze Circuit Lib Use Formally Verify Transf. Lib Add Key Is To Keep Track Of Every Step Start with a small block of the design Refine to next level Refinement Transformation Use cross-domain visibility to estimate impact on other domains Becomes a “Trusted” Transformation Document every design change (transformation)

13. Circuit Lib Add X Transf. Lib X X X X X Build And Use Design IP RepositoryStore Every New Circuit And Trusted Transformation Does not meet testability ! Does not meet area ! Use X Does not meet timing ! Add to the circuit lib Use Add Does not meet power !

15. The Revolution • Structured methodology that limits the space of exploration, yet achieves good results in the fixed time constraints of the design; • A formal mechanism for identifying the most critical hand-off points in the design chain; • A method for design re-use at all abstraction levels based on assembling and configuring platform components in a rapid and reliable fashion; • An intellectual framework for the complete electronic design process. Platform Based Design Integrated Design and Verification • Raise the level of abstraction by creating a high level model (HLM) • Successively refine the design ensuring that each refinement is equivalent to the previous one • Tightly integrate logic and physical design domains • Enable extensive use of a repository of trusted design transformations generated during the design process Transform Intractable CAD Engineering Problem Into Tractable SW Engineering Problem A. Sangiovanni-Vincentelli, DAC June 04 G. Spirakis, DATE Feb 04

16. Next Steps/Call to Action • New design flow based on Platform Based Design and IDV concepts must be developed • EDA industry must restructure its investment to embrace the new paradigm • Academia MUST lead this effort and make it THE design flow at all universities This is a Design Flow and SW Engineering problem NOT a traditional EDA problem