2009 itrs emerging research devices working group face to face meeting
Download
Skip this Video
Download Presentation
2009 ITRS Emerging Research Devices Working Group Face-to-Face Meeting

Loading in 2 Seconds...

play fullscreen
1 / 42

2009 ITRS Emerging Research Devices Working Group Face-to-Face Meeting - PowerPoint PPT Presentation


  • 144 Views
  • Uploaded on

2009 ITRS Emerging Research Devices Working Group Face-to-Face Meeting. Jim Hutchby - Facilitating San Francisco Hilton & Towers Hotel Franciscan A Room San Francisco, CA Sunday Dec 14, 2008 8:00 a.m. – 5:30 p.m. 2009 ITRS Emerging Research Devices Working Group Face-to-Face Meeting.

loader
I am the owner, or an agent authorized to act on behalf of the owner, of the copyrighted work described.
capcha
Download Presentation

PowerPoint Slideshow about ' 2009 ITRS Emerging Research Devices Working Group Face-to-Face Meeting' - mariko-ryan


An Image/Link below is provided (as is) to download presentation

Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author.While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server.


- - - - - - - - - - - - - - - - - - - - - - - - - - E N D - - - - - - - - - - - - - - - - - - - - - - - - - -
Presentation Transcript
2009 itrs emerging research devices working group face to face meeting

2009 ITRSEmerging Research DevicesWorking GroupFace-to-Face Meeting

Jim Hutchby - Facilitating

San Francisco Hilton & Towers Hotel

Franciscan A Room

San Francisco, CA

Sunday Dec 14, 2008

8:00 a.m. – 5:30 p.m.

2009 itrs emerging research devices working group face to face meeting1

2009 ITRSEmerging Research DevicesWorking GroupFace-to-Face Meeting

U-In Chung & Jim Hutchby - Facilitating

COEX InterContinental Hotel

Room Moderato I

Seoul, Korea

Saturday Dec 6, 2008

9:00 – 17:30

emerging research devices working group
Emerging Research Devices Working Group
  • Atsuhiro Kinoshita Toshiba
  • Dae-Hong Ko Yonsei U.
  • Hiroshi Kotaki Sharp
  • Atsuhiro Kinoshita Toshiba
  • Atsuhiro Kinoshita Toshiba
  • Franz Kreupl Qimonda
  • Nety Krishna AMAT
  • Zoran Krivokapic AMD
  • Phil Kuekes HP
  • Jong-Ho Lee Kyungpook Nation U.
  • Lou Lome IDA
  • Hiroshi Mizuta U. Southampton
  • Murali Muraldihar Freescale
  • Fumiyuki Nihei NEC
  • Ferdinand Peper NICT
  • Yaw Obeng NIST
  • Dave Roberts Air Products
  • Kaushal Singh AMAT
  • Sadas Shankar Intel
  • Satoshi Sugahara Tokyo Tech
  • Shin-ichi Takagi U. Tokyo
  • Ken Uchida Toshiba
  • Yasuo Wada Toyo U.
  • Rainer Waser RWTH A
  • Franz Widdershoven NXP
  • Jeff Welser NRI/IBM
  • Philip Wong Stanford U.
  • Kojiro Yagami Sony
  • David Yeh SRC/TI
  • In-Seok Yeo Samsung
  • In-K Yoo SAIT
  • Peter Zeitzoff Freescale
  • Yuegang Zhang LLLab
  • Victor Zhirnov SRC
  • Hiroyugi Akinaga AIST
  • Tetsuya Asai Hokkaido U.
  • Yuji Awano Fujitsu
  • George Bourianoff Intel
  • Michel Brillouet CEA/LETI
  • Joe Brewer U. Florida
  • John Carruthers PSU
  • Ralph Cavin SRC
  • U-In Chung Samsung
  • Byung Jin Cho KAIST
  • Sung WoongChung Hynix
  • Shamik Das Mitre
  • Erik DeBenedictis SNL
  • Simon Deleonibus LETI
  • Kristin De Meyer IMEC
  • Michael Frank AMD
  • Christian Gamrat CEA
  • Mike Garner Intel
  • Dan Hammerstrom PSU
  • Wilfried Haensch IBM
  • Tsuyoshi Hasegawa NIMS
  • Shigenori Hayashi Matsushita
  • Dan Herr SRC
  • Toshiro Hiramoto U. Tokyo
  • Matsuo Hidaka ISTEK
  • Jim Hutchby SRC
  • Adrian Ionescu ETH
  • Kohei Itoh Keio U.
  • Kiyoshi Kawabata Renesas Tech
  • Seiichiro Kawamura Selete
  • Rick Kiehl U. Minn
  • Suhwan Kim Seoul Nation U.
  • Hyoungjoon Kim Samsung
emerging research devices working group dec 6 th seoul fxf meeting objectives
Emerging Research Devices Working Group Dec. 6th Seoul FxF Meeting Objectives
  • Meet with Korean ERD Working Group (Morning)
    • Discuss International Collaboration Processes in 2009
    • ERD-Korean WG Inputs
      • 2007 Chapter Review – any Issues?
      • 2009 Scope and Content of Chapter
      • Other topics?
  • Meet with ERM (Afternoon)
    • Discuss ERM/ERD Interfaces & Collaboration in 2009
    • Review Proposed Materials & Device Topics for 2009
    • Discuss III-V and Ge Channel Replacement Materials?
    • Discuss new Potential Solutions section on “Carbon-based Nanoelectronics”
    • Devices in ERD-PIDs transition table - any entries limited by materials?
emerging research devices working group dec 6 nd seoul fxf meeting morning agenda
Emerging Research Devices Working Group Dec. 6nd Seoul FxF Meeting – Morning Agenda

9:00 Welcome and Introductions Drs. U-InChung &

J. Hutchby

9:15 Organization of Korean ERD & Dr. U-In Chung

Proposals from each part

9:20 ERD Logic part Prof. Jong-Ho Lee

9:50 ERD Memory part Dr. In-Seok Yeo

10:20 Break

10:50 ERD Architecture part Prof. Soo-Hwan Kim

11:20 Emerging Research Materials Prof. Dae-Hong Ko

12:00 Lunch

erd erm working groups joint meeting dec 6 th seoul fxf meeting afternoon agenda
ERD/ERM Working Groups Joint Meeting Dec. 6th Seoul FxF Meeting – Afternoon Agenda
  • 13:15 Review Arch’ture Approaches & Issues TBA
  • 13:45 Review Memory Device Issues TBA/V. Zhirnov
  • 14:30 Review Logic Device Issues G. Bourianoff
  • 15:15 Break
  • 15:30 Review/summarize ERM Workshops M. Garner
          • Workshops
          • ERM Tables
  • 16:30 Review Carbon-based Nanoelectronic M. Garner
  • materials issues
  • 17:00 Review proposed interaction with ERD M. Garner and
  • Working Group J. Hutchby
  • 17:30 Adjourn
kick off 2009 itrs erd chapter preparation dec 14 th san francisco fxf meeting objectives
Review Feedback on 2007 ERD Chapter

Review ERD Chapter Organization for 2009

Leadership

Mission and Scope

Deliverables, Timeline and Events

Chapter page count and page allocation

Operating Process and Meetings

Technology Entries Inclusion Criteria

Broadly inclusive

Maturity Metric (current publications)

Kick off 2009 ITRS ERD Chapter Preparation Dec. 14th San Francisco FxF Meeting Objectives
kick off 2009 itrs erd chapter preparation dec 14 th san francisco fxf meeting objectives1
Review ERD Chapter Content for 2009

Major Technical Sections

Architectures

Logic Devices

Selected Emerging Technologies

Compliment or Extend CMOS

Beyond CMOS

Potential Solutions

Memory Devices

Selected Emerging Technologies

Selected Potential Solutions

Critical Review and Guiding Principle Sections

Critical Review

Selected Memory Devices

Selected Logic Devices

Guiding Principles

Review ERD Decisions & Action Items for 2009

Kick off 2009 ITRS ERD Chapter Preparation Dec. 14th San Francisco FxF Meeting Objectives
kick off 2009 itrs erd chapter preparation dec 14 th san francisco fxf meeting agenda
7:30 Continental Breakfast

8:00 Introductions

8:10 Review meeting objectives and agenda J. Hutchby

8:20 Review ERD Organization for 2009 J. Hutchby

Leadership

Mission/Charter and Scope

Deliverables, Timeline, and Events

Chapter Page Count and Page Allocation

Operating Process and Meetings

9:00 Review status of ERD J. Hutchby

Chapter Status & Organization

2007 ERD Chapter Feedback (12/07)

Decisions for 2009

10:00 Break

Kick off 2009 ITRS ERD Chapter Preparation Dec. 14th San Francisco FxF Meeting Agenda
kick off 2009 itrs erd chapter preparation dec 14 th san francisco fxf meeting agenda1
10:15 Review ERD Workshops and Discuss

Status of Materials, Devices & Architectures

10:15 Materials M. Garner

11:00 Memory Devices V. Zhirnov

12:15 Lunch (Continue Discussion)

12:45 Logic Devices G. Bourianoff

Complement or extend CMOS

Beyond CMOS

2:15 Architectures R. Cavin

3:15 Break

3:30 Discuss Critical Review & Guiding Principle Sections

3:30 Critical Review J Hutchby

Memory Devices

Logic Devices

4:30 Guiding Principles J. Hutchby

5:00 Wrap up, Review Decisions and Actions Required J. Hutchby

5:30 Adjourn

Kick off 2009 ITRS ERD Chapter Preparation Dec. 14th San Francisco FxF Meeting Agenda
mission charter of erd chapter
On behalf of the 2009 ITRS, develop an Emerging Research Devices chapter to --

Critically assess suitability and maturity of novel approaches/technologies for Information Processing technology intended to complement or extend ultimate CMOS

Identify the most promising approach(es) to Information Processing technology to be implemented by 2022

To offer substantive input and guidance to –

Global research community

Relevant government agencies

Technology managers

Suppliers

Mission/Charter of ERD Chapter
scope of erd chapter
Integrated emerging research memory, logic and new architecture technologies enabled by supporting --

Materials and process technologies

Modeling and simulation

Metrologies

Technology Entries will be selected based on level of published research activity, credibility and progress

Should show significant maturity in research domain

Further adoption limited by research issues

Scope of ERD Chapter
scope of erd chapter criteria for including technology entries
Research Devices and Architectures –

Published by 2 or more groups in archival literature and peer reviewed conferences, or

Published extensively by 1 group in archival literature and peer reviewed conferences

Scope of ERD ChapterCriteria for Including Technology Entries
slide14
Provides a valuable macro function more efficiently than CMOS

Energy restorative process (e.g. gain)

Functionally interfaceable with CMOS

At or above room temperature operation

Minimum energy per functional operation

Minimum, scalable cost per function

Scope of ERD Chapter Fundamental Requirements for CMOS Extension Information Processing Technologies
slide15
Information processing throughput orders of magnitude beyond ultimately scaled CMOS

Energy restorative process (e.g. gain)

Functionally compatible with CMOS

At or above room temperature operation

Reduced energy per functional operation

Reduced, scalable cost per function

Scope of ERD Chapter Fundamental Requirements for Beyond CMOS Information Processing Technology Entries
proposed 2009 erd working group organization
ERD Function Leader

Chapter Chair – North America Hutchby

Chapter Co-chair – Europe TBD

Chapter Co-chair – Japan ERD Hiramoto

Chapter Co-chair – Korea ERD Chung

Memory Zhirnov

Logic Bourianoff

Architecture Cavin

Editorial Team Hutchby, Bourianoff, Cavin, Chung, Garner/Herr, Hiramoto, Zhirnov

ITRS Liaisons

PIDS Ng, Hutchby

FEP Herr

Modeling & Simulation Shankar

Materials Shankar

Metrology Herr

Design Yeh/Bourianoff

More than Moore Brillouet

Proposed 2009 ERD Working Group Organization
2009 itrs erd major deliverables and timeline
ERD Chapter due August 21, 2009

Major Tasks and Time Line

Outlines for Memory, Logic, Architecture, Mat’l March 18

Technology Requirements Tables April 6

Guiding Principles Section June 1

Draft Text Completed

Memory, Logic, Architecture, Material July 6

Functional Organization & Critical Review July 20

Scope, Difficult Challenges, etc. July 27

Chapter Completed August 21

Chapter Frozen Sept. 15

Major Face-to-Face Meetings in 2009

ITRS/ERD Meeting near Brussels, Belgium March 18

ITRS/ERD Meeting at Semicon West (SF, CA) July 12

ITRS/ERD Meeting near Hsinchu, Taiwan Nov. 30

2009 ITRS/ERD Major Deliverables and Timeline
2008 erd erm workshops
2008 ERD/ERM Workshops

Done

Done

Done

Done

Done

draft erd chapter outline
Scope (1 page)

Difficult Challenges (1)

Taxonomy Chart (1)

Devices

Memory Devices (15)

Logic Devices (15)

Architectures (8)

Critical Assessment (6)

Fundamental Guiding Principles (3)

Total Pages (50)

Draft ERD Chapter Outline

DRAFT

feedback on 2007 erd chapter overall comments
Feedback on 2007 ERD Chapter Overall Comments
  • Increase involvement of international members – strengthen ties between US – EU – Asia. Requires good balance of representing members from these three regions.
  • Mission of ERD is not clear cut to universities – clearly state the mission in the introduction.
  • Need more detailed discussion of key messages and issues between ERD and ERM
  • To what extent and how does ERD/ERM deal with More than Moore?
  • Need a metric to gauge the potential of each Technology Entry to be disruptive.
  • Is a Technology Entry being limited by Fundamental Limits or a technologically limited research gap?
  • ERD needs to maintain a dialog with the Systems Drivers Chapter
  • Should ERD continue to include a failing Technology Entry?
feedback on 2007 erd chapter emerging research memory devices
Feedback on 2007 ERD ChapterEmerging Research Memory Devices
  • Transfers
    • Engineered Tunnel Barrier Memory to PIDS and FEP
    • Keep the Ferroelectric FET Memory Technology in ERD
    • Include STT RAM as a new entry. Given progress, should we include STT RAM in a new Potential Solution Table for Memory Technologies?
  • Other comments
    • Re-combine the capacitive and resistive memory tables
    • Discuss other materials (in addition to Pt/NiO/Pt) for Fuse/Anti-fuse Memory
    • Try to elucidate fundamental limits of Memory Devices
    • Add a new row to memory table to include Storage Capacity
    • Address Memory Architecture, perhaps in the Architecture Section
    • Why do all the memory technology entries have for “Best Projected Write Cycles” a value of 3E16 ?
    • Include scaling projections for all Memory Technology Entries
    • The Memory Group is preparing a single reference document containing scaling projections and citations
feedback on 2007 erd chapter emerging research logic devices 1 3
Feedback on 2007 ERD ChapterEmerging Research Logic Devices (1/3)
  • Transfers proposed
    • III-V Alternate Channel Materials to PIDS/FEP and
    • Low Dimensional Materials to PIDS/FEP
    • Move Molecular Devices to the Transition Table.
    • Include Band-to-Band Tunneling Device category in Table 1.
    • Move RTD out of Table 2 to Transition Table
  • Other comments
    • The comprehensive review with references is important
    • Like having two tables to represent the traditional, digital Boolean device applications and the new table to represent new, perhaps analog, applications of emerging research devices.
    • Include chart entitled “Evolution of Extended CMOS” from Japan ERD
    • The best demonstrated parameters are obtained from different devices. Is it possible to obtain them simultaneously on one device? We should include a note to this effect.
    • Define “Switching Speed” and “Circuit Speed”
feedback on 2007 erd chapter emerging research logic devices 2 3
Feedback on 2007 ERD ChapterEmerging Research Logic Devices (2/3)
  • Other comments
    • Discuss “Spin Gain Transistor” and “Spin Torque Transistor” in text. “Single Spin device” is not in the table
    • Should we constrain Logic Technology by availability of Memory Tech?
    • Should use term “high mobility/high velocity” instead of “high mobility”
    • Improve linkages to the Architecture Section and to the System Drivers Chapter.
    • Increase emphasis on Table 2 while maintaining Table 1. Place a stronger emphasis on non-linear response functions. Think about how to amend Table 1 to differentiate “Beyond CMOS” devices.
    • Separate Spin FETs from Spin State Devices (Spin transport without charge transport) and evaluate as separate categories.
    • Divide Table 1 into 2 tables – one for CMOS extension and the other for Beyond CMOS?
    • Include Spin Wave Bus in Table 1?
feedback on 2007 erd chapter emerging research logic devices 3 3
Feedback on 2007 ERD ChapterEmerging Research Logic Devices (3/3)
  • Other comments
    • Keep SETs in Table 2, Alternative Information Processing Technologies
    • Change Multiferroic Tunnel Junction Devices to Multiferroic Switching Device and keep in Table 2.
feedback on 2007 erd chapter emerging research architectures
Feedback on 2007 ERD ChapterEmerging Research Architectures
  • Transfers proposed
    • Should we continue the “Homogeneous Multicore Section
  • Other comments
    • Morphic Architectures might include: Associative Memory Processor; Cellular Nonlinear Networks; and Neuromorphic LSIs for collision avoid.
    • Should Emerging Memory Architectures be addressed in this Section?
    • Recommend evaluation of integrating energy sources, storage memory, low-power sensors, and computational engines
    • Consider using biological concepts for new architectures to obtain high energy efficiency.
    • Consider integration of biological elements
feedback on 2007 erd chapter critique section for memory logic tech entries
Feedback on 2007 ERD ChapterCritique Section for Memory &Logic Tech Entries
  • Comments
    • Important section to survey technology trend of emerging research devices
    • Standard Deviation is very helpful
    • How and why were the Evaluation Criteria chosen?
    • Need much more discussion of the data.
    • How can we critically review Architectural approaches? Should we try?
    • Should we use different colors because our use of red, white and yellow has a different meaning than the use of these colors in other chapters of the ITRS.
    • We need to sure our Critique Section analysis is consistent with the text for the Technology Entries, e.g., we need to be sure the highs and lows in the Critique are addressed as strengths and research gaps in the text sections.
feedback on 2007 erd chapter scope difficult challenges taxonomy guiding principles
Feedback on 2007 ERD ChapterScope, Difficult Challenges, Taxonomy & Guiding Principles
  • Scope: In general the Scope is very good. However, the statement “…, CMOS certainly will provide a platform processing technology for sometime beyond the end of dimensional scaling, exploiting the notion that the ultimately scaled MOSFET is a nearly ideal electronic charge-based device” is a rather strong statement. Is it too strong? Should we say something about the technology “cost” in the Scope?
  • Difficult Challenges: The Difficult Challenges are very good.
  • Guiding Principles
    • The five original Guiding Principles are very good.
    • The sixth Guiding Principle related to “Architecture” needs clarification as to whether it only applies to “Beyond CMOS” or to both “Beyond CMOS” and CMOS integrated with Beyond CMOS devices?That is do we address: (1) New architectures with conventional devices and/or (2) New architectures with beyond CMOS devices on CMOS infrastructure?.
decisions for 2009 chapter
Decisions for 2009 Chapter
  • Memory
    • Include device structural aspects of the new NW PCRAM in ERD with a summary of the materials issues. Include more materials information in ERM on this topic.
    • Include the Spin Torque Transfer MRAM in ERD/ERM.
    • Decide whether or not to include the “Magnetic Domain” or “Racetrack Memory” in ERD. We need to focus on mP applications.
    • We will keep nanomechanical memory in ERD Memory Table.
    • Move the Ferroelectric Effects Tunneling Barrier Memory from the Electronic Effects Memory category to the Memory Transition Table
    • Leave “Redox type” memories in the ERD. These are different than ionic cation migration effects memory.
    • By categorizing using a physics-based system, a given material that exhibits 2 or more effects will be listed in each category.
decisions for 2009 chapter1
Decisions for 2009 Chapter
  • Logic
    • ERD/ERM recommends carbon-based nanoelectronics to include CNT, graphene for more resources and roadmapping for IRC as part of promising technologies for 5-10 years demonstration horizon
    • Carbon-based nanoelectronics will be included in the 2009 ERD chapter via a two new Potential Solutions tables – for materials and for device issues.
    • Seven potential technologies were considered:
        • Carbon-based Nanoelectronics
        • Collective spin
        • Spin torque transfer
        • Atomic and electrochemical metal
        • CMOL/FPNI
        • Single Electron Transistor
        • NEMS
comments 9 23 08
Comments 9/23/08
  • Does this include wires, vias, pkg technology, etc. – no
  • For emphasis on Carbon-based NE Mike will connect w/ ESH Jim Jewett
  • ERM Table of Applications & Proposed Structure
    • What is infrastructure mean?
    • Equipment issue is important.
  • Potential Solution Chart
    • Don’t tie down the time frame too rigidly
    • Label chart by material or device structure
    • Label as More Moore and Beyond CMOS
    • Can we have a memory driver as we have a logic driver?
    • Entries
slide33

Critical Review on Critical Assessment

F. Nihey (NEC)

1. Changes in Critical Assessment(2007<->2005)

2. Short Comments

slide34

ERD - Critical Assessment - Memory

Engineered Tunnel Barrier

Fuse/Anti-Fuse

Nano Mechanical

Nano Floating Gate

Engineered Tunnel Barrier

Electron Injection

Ferroelectric FET

Insulator Resistance Change

Polymer

Ionic

Molecular

2005 Edition

Ferroelectric FET

Macromolecular

Molecular

2007 Edition

slide35

ERD – Critical Assessment - Logic

Engineered Tunnel Barrier

1D Structure

Channel Replacement Mat.

Single Electron Tunneling

1D Structure

Resonant Tunneling

Single Electron Tunneling

Molecular

Molecular

Ferromagnetic

Spin

2005 Edition

Ferromagnetic

Spin

2007 Edition

slide36

Evaluation - Memory

2005

2007

2005

2007

2005

2005

2007

2007

slide37

Evaluation – Logic (1/2)

2005

2007

2005

2007

2005

2007

critical review memory
How can be improved? Something missing? Other comments?

Suggestions:

for each memory candidate, include very short comments (arguments!) on the high-scored and low-scored features: main advantages versus open issues(when possible quantify comments).

when applicable, for each memory candidate, short comment about level of concrete demonstration and/or prospects for NV, SRAM, DRAM

identify contributors.

Critical review: memory
critical review overview

Team:

  • Jim Hutchby et al, Reviewer: Adrian M. Ionescu
  • Goals:
    • assess each Technology Entry (TE) for Memory & Logic
    • compare/benchmark with/against:
      • Si CMOS logic
      • memory technology to displace
    • provide the ERD community with and funding agencies with ERD WG collective view of the overall (long term) potential of each TE

Critical Review: overview

slide41

> 20

>16 - 18

>18 - 20

< 16

Critical Review – Memory (1/2)

3

2

1

3

2

1

3

2

1

3

2

1

slide42

> 20

>16 - 18

>18 - 20

< 16

Critical Review – Memory (2/2)

3

2

1

3

2

1

3

2

1

3

2

1

ad