1 / 47

THE INVERTERS

THE INVERTERS. DIGITAL GATES Fundamental Parameters. Functionality Reliability, Robustness Area Performance Speed (delay) Power Consumption Energy. Noise in Digital Integrated Circuits. DC Operation: Voltage Transfer Characteristic. Mapping between analog and digital signals.

marguerite
Download Presentation

THE INVERTERS

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. THE INVERTERS

  2. DIGITAL GATES Fundamental Parameters • Functionality • Reliability, Robustness • Area • Performance • Speed (delay) • Power Consumption • Energy

  3. Noise in Digital Integrated Circuits

  4. DC Operation: Voltage Transfer Characteristic

  5. Mapping between analog and digital signals

  6. Definition of Noise Margins

  7. The Regenerative Property

  8. Fan-in and Fan-out

  9. The Ideal Gate

  10. VTC of Real Inverter

  11. Delay Definitions

  12. Ring Oscillator

  13. Power Dissipation

  14. CMOS INVERTER

  15. The CMOS Inverter: A First Glance

  16. V DD PMOS Metal1 Polysilicon NMOS CMOS Inverters 1.2 m m =2l Out In GND

  17. Switch Model of CMOS Transistor

  18. CMOS Inverter: Steady State Response

  19. CMOS Inverter: Transient Response

  20. CMOS Properties • Full rail-to-rail swing • Symmetrical VTC • Propagation delay function of load capacitance and resistance of transistors • No static power dissipation • Direct path current during switching

  21. Voltage TransferCharacteristic

  22. I Dn V = V -V in DD GSp I = - I Dn Dp V = V -V out DD DSp V out I I I Dp Dn Dn V =0 V =0 in in V =3 V =3 in in V V V DSp DSp out V =-2 GSp V =-5 GSp V = V -V V = V -V in DD GSp out DD DSp I = - I Dn Dp PMOS Load Lines

  23. CMOS Inverter Load Characteristics

  24. CMOS Inverter VTC

  25. Simulated VTC

  26. Gate Switching Threshold

  27. MOS Transistor Small Signal Model

  28. Determining VIH and VIL

  29. Propagation Delay

  30. CMOS Inverter: Transient Response

  31. CMOS Inverter Propagation Delay

  32. Computing the Capacitances

  33. V DD PMOS Metal1 Polysilicon NMOS CMOS Inverters 1.2 m m =2l Out In GND

  34. The Miller Effect

  35. Computing the Capacitances

  36. Impact of Rise Time on Delay

  37. Delay as a function of VDD

  38. Where Does Power Go in CMOS?

  39. Vdd Vin Vout C L Dynamic Power Dissipation 2 Energy/transition = C * V L dd 2 Power = Energy/transition * f = C * V * f L dd Not a function of transistor sizes! Need to reduce C , V , and f to reduce power. L dd

  40. Impact ofTechnology Scaling

  41. Technology Evolution

  42. Technology Scaling (1) Minimum Feature Size

  43. Technology Scaling (2) Number of components per chip

  44. Propagation Delay Scaling

  45. Technology Scaling Models

  46. Scaling Relationships for Long Channel Devices

  47. Scaling of Short Channel Devices

More Related