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Chapitre 3 Les Instructions des processeurs

Chapitre 3 Les Instructions des processeurs. Opcode. Oprd. 1. Oprd. 2. Result. Next. Opcode. Oprd. 1. Oprd. 2. Next 1. Next 2. Generic Instructions. Type 1 : Data Handling. Type 2 : Control. ! Inefficient : address of next instruction is stored in each instruction.

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Chapitre 3 Les Instructions des processeurs

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  1. Chapitre 3 Les Instructions des processeurs

  2. Opcode Oprd. 1 Oprd. 2 Result Next Opcode Oprd. 1 Oprd. 2 Next 1 Next 2 Generic Instructions Type 1 : Data Handling Type 2 : Control ! Inefficient : address of next instruction is stored in each instruction.

  3. Von Neumann Bottleneck For each data handling instruction : Central Processing Unit opcode 4 addresses 2 operands Central Memory result

  4. Program Counter Very often next instruction follows current one Program Memory Control Unit P register + 1 X I register

  5. Program Counter (2) Type 1 : Data Handling Opcode Oprd. 1 Oprd. 2 Result Type 2 : Control Opcode Oprd. 1 Oprd. 2 Next 1 Default next address is computed in P register

  6. Stack Oprd. 1 / Res. Oprd. 2 Expression evaluation : Default postion of operand(s) and result(s) is on the stack . . .

  7. Transfer Instruction Data Handling Opcode Oprd. 1 Oprd. 2 Result Data Transfer Push/Pop Operand

  8. Expression Evaluation a * ( b + c * d ) / ( e + f ) --->a b c d * + * e f + / d c * d b + c * d a*(b + c * d) c b a b a a

  9. Expression Evaluation (2) a * ( b + c * d ) / ( e + f ) --->a b c d * + * e f + / f e + f a*(b + c * d) / (e + f) e a*(b + c * d) a*(b + c * d)

  10. 0 vs. 3 addresses c := a + b 0 addresses pusha pushb add popc 3 addresses adda,b,c Efficiency depends on type of program

  11. Load/Store Reg Memory Address Registers Insert a limited number of addressable registers in the CPU to store intermediate results New data transfer instruction format

  12. Registers (2) Data handling instructions become : 3 address Opcode Op 1 Op 2 Res 2 address Opcode Op 1& Res Op 2

  13. Vector Instructions When the same operation has to be performed on all elements of a vector Opcode Oprd. 1 (1st elt.) Oprd. 2 (1st elt.) Result (1st elt.) Count Applications : Block move in 1 or more dimensions Arithmetic and Logic operations

  14. Vector Instructions Semantics : i : = 0 Result[i] := Oprd1[i] op Oprd2[i] i := i + 1 i ?=? Count no yes

  15. Type Management Memory contains : • Instructions • Pointers (addresses) • Integer Numbers • Floating Point Numbers • Double Precision Integer Numbers • Double Precision Floating Point Numbers • Characters • Character strings • . . .

  16. Data Type Management One possibility : 1 opcode for each data type ConvInt32Real32 ConvInt32Real64 ConvInt32Int64 ConvReal64Real32 . . . AddInt32 AddInt64 AddReal32 AddReal64 . . . Data type is encoded implicitly in opcode

  17. Tagged Memory Second possibility : explicitly store type with data item tag data 0 0 0 Instruction 0 0 1 Pointer 0 1 0 Integer32 0 1 1 Floating Point Number 1 0 0 Integer64 . . . . . . Result : shorter instructions, but more memory . . .

  18. Condition Code Register Goal : shorten control instructions Opcode Oprd. 1 Oprd. 2 Next Into : Opcode Cond Next Z N V C evaluated  instruction

  19. Subroutine Obsolete strategy : xyz : jmp abc 1 4 jsr xyz abc : 2 3 jmp xyz Problems : recursion re-entrance

  20. xyz : 1 jsr xyz 2 abc : abc return Subroutine Actual Implementation

  21. . . . . . . xyz : 1 2, 3 jsr xyz 4 abc : jsr xyz rst: rst rst return abc . . . Subroutine : Recursion . . . . . .

  22. Addressing Modes How is the operand/result named ? Direct Addressing xyz xyz : Examples : jump simple operands memory

  23. Addressing Modes (2) Indirect Addressing rst : xyz xyz : rst Examples : pointers call by variable . . . memory

  24. xyz Addressing Modes (3) Indirect Addressing (Register) R R: xyz : Examples : pointers call by variable stack in central memory . . . memory

  25. Addressing Modes (4) Relative addressing offset + base Examples : Array Record Relative jump memory

  26. Block Structured Languages A program is a set of nested blocks BEGIN ... END RED; BEGIN ... END GREEN; BEGIN ... END PURPLE; BEGIN ... END BLUE.

  27. Block Structured Languages A program is a set of nested blocks { ... } /* RED */; { ... } /* GREEN */; { ... } /* PURPLE */; { ... } /* BLUE */.

  28. Block Structured Languages An identifier can be used everywhere within the block where it is declared VAR A: CARDINAL; VAR B: REAL; VAR C: CHAR; { ... A:=...; B:=...; C:=...; ... END RED; X { ... A:=...; B:=...; C:=...; ... END GREEN; X { ... A:=...; B:=...; C:=...; ... END PURPLE; X X { ... A:=...; B:=...; C:=...; ... END BLUE.

  29. Block Structured Languages A global identifier can be redefined The local definition dominates VAR A: CARDINAL; VAR B: REAL; VAR A,C: CHAR; BEGIN ... A:="$"; B:=...; C:=...; ... END RED; BEGIN ... A:= 1; B:=...;... END GREEN; BEGIN ... A:= 2; B:=...; END PURPLE; BEGIN ... A:= 3;... END BLUE.

  30. Variables are declared in a Block Their address has two parts: The identifier of the block The position in that block (offset) Block identifiers can be expressed by specifying relative nesting levels Block id. Rel.nesting level Offset Offset Data Addressesin Block Structured Languages

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