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INTRODUCTION

INTRODUCTION. ARM is a RISC processor . It is used for small size and high performance applications . Simple architecture – low power consumption . TIMELINE (1/2). 1985: Acorn Computer Group manufactures the first commercial RISC microprocessor .

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INTRODUCTION

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  1. INTRODUCTION • ARM is aRISC processor. • It is used for small size and high performance applications. • Simple architecture – low power consumption. ARM System - On - Chip Architecture

  2. TIMELINE(1/2) • 1985: Acorn Computer Group manufactures the first commercialRISC microprocessor. • 1990: Acorn andAppleparticipation leads to the founding of Advanced RISC Machines (A.R.M.). • 1991: ARM6,Firstembeddable RISC microprocessor. • 1992 – 1994: Various companies use ARM (Sharp, Samsung), while in 1993 ARM7, the first multimedia microprocessor is introduced. ARM System - On - Chip Architecture

  3. TIMELINE(2/2) • 1995: Introduction of Thumb andARM8. • 1996 – 2000: Alcatel, Huindai, Philips, Sony, use ΑRM, while in 1999 η ARM cooperates withErickson for the development of Bluetooth. • 2000 – 2002: ARM’s share of the 32 – bit embedded RISC microprocessor market is 80%. ARM Developer Suite is introduced. ARM System - On - Chip Architecture

  4. THE ARM ARCHITECTURE

  5. GENERAL INFO (1/2) AIM: Simple design • Load – store architecture • 32 bit data bus • 3 addressing modes ARM System - On - Chip Architecture

  6. Simple architecture+ Simple instruction set + Code density Small size Low power consumption GENERAL INFO (2/2) ARM System - On - Chip Architecture

  7. Registers • 32 general purpose registers • 7 modes of operation • Different set of visibleregisters and differentcpsr control level in each mode. ARM System - On - Chip Architecture

  8. ARM Programming Model r0 usable in user mode r1 r2 r3 system modes only r4 r5 r6 r7 r8_fiq r8 r9_fiq r9 r10_fiq r10 r1 1_fiq r1 1 r13_und r12_fiq r13_irq r12 r13_abt r13_svc r14_und r13_fiq r14_irq r13 r14_abt r14_svc r14_fiq r14 r15 (PC) SPSR_und SPSR_irq SPSR_abt CPSR SPSR_svc SPSR_fiq svc abort irq undefi ned fiq user mode mode mode mode mode mode

  9. CPSR N: Negative Z: Zero C: Carry V: Overflow Q: Saturation (for enhanced DSP instructions) ARM CPSR format ARM System - On - Chip Architecture

  10. Memory Organization • Address bus: 32 – bits • 1 word = 32 – bits ARM System - On - Chip Architecture

  11. Instruction Set • Three instruction types • Data processing • Data transfer • Control flow ARM System - On - Chip Architecture

  12. Supervisor mode • In user modethe operating system handles operations outside user privileges. • Using“supervisor calls”, the user goes to system level and can perform system functions. ARM System - On - Chip Architecture

  13. I/O System • ARMhandles peripherals as“memory mapped devices with interrupt support”. • Interrupts: • IRQ: normal interrupt • FIQ: fast interrupt ARM System - On - Chip Architecture

  14. Exceptions • Exceptions: • Interrupts • Supervisor Call • Traps • When an exception takes place: • The value of PC is copied tor14_exc • Theoperating mode changes into the respective exception mode. • The PC takes theexception handlervector address. ARM System - On - Chip Architecture

  15. ARM programming model r0 usable in user mode r1 r2 r3 system modes only r4 r5 r6 r7 r8_fiq r8 r9_fiq r9 r10_fiq r10 r1 1_fiq r1 1 r13_und r12_fiq r13_irq r12 r13_abt r13_svc r14_und r13_fiq r14_irq r13 r14_abt r14_svc r14_fiq r14 r15 (PC) SPSR_und SPSR_irq SPSR_abt CPSR SPSR_svc SPSR_fiq svc abort irq undefi ned fiq user mode mode mode mode mode mode

  16. THE ARM INSTRUCTION SET

  17. Data Processing Instructions (1/2) • Arithmetic Operations ADD r0, r1, r2 ; r0:= r1+r2 and don’t update flags ADDS r0, r1, r2 ; r0:= r1+r2 and update flags • Logical Operations AND r0, r1, r2 ; r0:= r1 AND r2 • Register Movement MOV r0, r2 • Comparison CMP r1, r2 ARM System - On - Chip Architecture

  18. Data Processing Instructions (2/2) • Operands: • Immediate operands ADD r3, r3, #1 • Shifted register operands: ADD r3, r2, r1, LSL #3 • Miscellaneous data processing instructions: • Multiplication: MUL r4, r3, r2 ARM System - On - Chip Architecture

  19. Data transfer instructions • Load and store instructions: LDR r0, [r1] STR r0, [r1] • Offset: LDR r0, [r1,#4] • Post – indexed: LDR r0, [r1], #16 • Auto – indexed: LDR r0, [r1,#16]! • Multiple data transfers: LDMIA r1, {r0,r2,r5} ARM System - On - Chip Architecture

  20. Examples • PRE: • r0 = 0x00000000 • r1 = 0x00009000 • mem32[0x00009000] = 0x01010101 • mem32[0x00009004] = 0x02020202 • LDR r0, [r1, #4]! • POST: • r0 = 0x02020202 • r1 = 0x00009004 ARM System - On - Chip Architecture

  21. Examples • PRE: • r0 = 0x00000000 • r1 = 0x00009000 • mem32[0x00009000] = 0x01010101 • mem32[0x00009004] = 0x02020202 • LDR r0, [r1, #4] • POST: • r0 = 0x02020202 • r1 = 0x00009000 ARM System - On - Chip Architecture

  22. Examples • PRE: • r0 = 0x00000000 • r1 = 0x00009000 • mem32[0x00009000] = 0x01010101 • mem32[0x00009004] = 0x02020202 • LDR r0, [r1], #4 • POST: • r0 = 0x01010101 • r1 = 0x00009004 ARM System - On - Chip Architecture

  23. Examples • mem32[0x80018] = 0x03 • mem32[0x80014] = 0x02 • mem32[0x80010] = 0x01 • r0 = 0x00080010 LDMIA r0!, {r1-r3} • r0 = 0x0008001c • r1 = 0x00000001 • r2 = 0x00000002 • r3 = 0x00000003 ARM System - On - Chip Architecture

  24. Examples • mem32[0x8001c] = 0x04 • mem32[0x80018] = 0x03 • mem32[0x80014] = 0x02 • mem32[0x80010] = 0x01 • r0 = 0x00080010 LDMIB r0!, {r1-r3} • r0 = 0x0008001c • r1 = 0x00000002 • r2 = 0x00000003 • r3 = 0x00000004 ARM System - On - Chip Architecture

  25. Conditional execution • Instructions can be executed conditionally without braches CMP r2, r3 ;subtract and set flags ADDGE r4, r5, r6 ; if r2>r3 SUBLT r4, r5, r6 ; else ARM System - On - Chip Architecture

  26. Conditional execution mnemonics ARM System - On - Chip Architecture

  27. Control flow instructions • Branch instruction: B label • Conditional branch: BNE label • Branch and Link: BL label BL loop … … Loop … … … … MOV PC, r14 ; επιστροφή ARM System - On - Chip Architecture

  28. Example 1 AREA ARMex, CODE, READONLY; Name this block of code ARMex ENTRY ; Mark first instruction to execute start MOV r0, #10 ; Set up parameters MOV r1, #3 ADD r0, r0, r1 ; r0 = r0 + r1 stop MOV r0, #0x18 ; angel_SWIreason_ReportException LDR r1, =0x20026 ; ADP_Stopped_ApplicationExit SWI 0x123456 ; ARM semihosting SWI END ; Mark end of file ARM System - On - Chip Architecture

  29. Example 2 AREA subrout, CODE, READONLY; Name this block of code ENTRY ; Mark first instruction to execute start MOV r0, #10 ; Set up parameters MOV r1, #3 BL doadd ; Call subroutine stop MOV r0, #0x18 ; angel_SWIreason_ReportException LDR r1, =0x20026 ; ADP_Stopped_ApplicationExit SWI 0x123456 ; ARM semihosting SWI doadd ADD r0, r0, r1 ; Subroutine code MOV pc, lr ; Return from subroutine END ; Mark end of file ARM System - On - Chip Architecture

  30. ARMORGANIZATION AND IMPLEMENTATION

  31. 3 – Stage Pipeline (ARM7 – 80MHz) • Fetch • Decode • Execute • Throughput: 1 instruction / cycle

  32. 5 – stage pipeline (1/2) • Program execution time: • Ways to reduce : • IncreaseLogic simplification • ReduceCPIreduce the number of multicycle instructions. ARM System - On - Chip Architecture

  33. 5 – stage pipeline (ARM9-150MHz) (2/2) • Fetch • Decode • Execute • Buffer / Data • Write - Back

  34. ARM coprocessor interface • ARM supports upto 16 coprocessors, which can be software emulated. • Each coprocessor has upto 16 general-purpose registers • ARM is aload and store architecture. • Coprocessors usually handleon – chip functions, such ascache andmemory management. ARM System - On - Chip Architecture

  35. ARCHITECTURAL SUPPORT FOR HIGH – LEVEL LANGUAGES

  36. Floating - point accelerator (1/2) • For floating-point operations, ARM has theFPEsoftware emulator and theFPA 10 hardware floating – point accelerator. • FPA 10 includes: • Coprocessor interface • Load / store unit • Register bank ( 8 registers 80 – bit ) • ALU (adder, mult, div) ARM System - On - Chip Architecture

  37. Floating - point accelerator (2/2) ARM System - On - Chip Architecture

  38. APCS (1/2) • APCS (ARM Procedure Call Standard) is a set of rules concerning C procedure input and output. • Specific use ofgeneral purpose registers. (r0 – r4: arguments, r4 – r8 variables, r10 stack limit, etc. ) • Procedure I/O: BL Loop … Loop … MOV pc, lr ARM System - On - Chip Architecture

  39. APCS (2/2) Assembly code f1 LDR r0, [r13] STR r13!, [r14] STR r13!, [r0] BL f2 SUB r13,#4 LDR r13!, r15 C code void f1(int a) { f2(a); } 16 8 4 0 Stack pointer ARM System - On - Chip Architecture

  40. THUMB PROGRAMMER’S MODEL

  41. General information • Thumb objective: Code density. • Thumb has a 16 – bit instruction set. • A subset of the ARM instruction set is coded to a 16–bit space • With appropriate use great benefits can be achieved in terms of • Power efficiency • Enhanced performance ARM System - On - Chip Architecture

  42. Going in and out ofThumb mode • Using theBX instruction, in ARM state: e.g. ΒΧ r0 • Commands are assembled as 16 – bit instructions with the appropriate directive • Ifr0[0] is 1, the T bit in theCPSR becomes 1 and thePC is set to the address obtained from the remaining bits ofr0. • Using the BX instruction fromThumb state, we return toARM state. ARM System - On - Chip Architecture

  43. The Thumb programmer’s model • Thumb registers ARM System - On - Chip Architecture

  44. Thumb Upto 70% code size reduction 40% more instructions. 45% faster code with 16-bit memory Requiresabout 30% less external memory ARM 40% faster code when coupled with a 32-bit memory ARM vs. Thumb(1/3) ARM System - On - Chip Architecture

  45. If performance is critical: ARM If cost and power consumption are critical: Thumb ARM vs.Thumb(2/3) ARM System - On - Chip Architecture

  46. ARM and Τhumb interaction • A 32 – bit ARM system can go into Thumb mode for specific routines, in order to meet power and memory constraints. • A 16 – bit system: Can use anon – chip, 32 – bit memory forARM state routines, and a 16-bitoff – chip memory andThumb code for the rest of the application. ARM System - On - Chip Architecture

  47. Example 3 AREA ThumbSub, CODE, READONLY ; Name this block of code ENTRY ; Mark first instruction to execute CODE32 ; Subsequent instructions are ARM header ADR r0, start + 1 ; Processor starts in ARM state, BX r0 ; so small ARM code header used ; to call Thumb main program CODE16 ; Subsequent instructions are Thumb start MOV r0, #10 ; Set up parameters MOV r1, #3 BL doadd ; Call subroutine stop MOV r0, #0x18 ; angel_SWIreason_ReportException LDR r1, =0x20026 ; ADP_Stopped_ApplicationExit SWI 0xAB ; Thumb semihosting SWI doadd ADD r0, r0, r1; Subroutine code MOV pc, lr ; Return from subroutine END ; Mark end of file ARM System - On - Chip Architecture

  48. Example 4 • Implement the following pseudocode in ARM and Thumb assembly. Which is more efficient in terms of execution time and which in terms of code size? If r1>r2 then R3= r4 + r5 R6 = r4 – r5 Else R3= r4 - r5 R6 = r4 + r5 ARM System - On - Chip Architecture

  49. Example 5 • Write an ARM assembly program that loads data from memory location 0x40, sets bits 3 to 5, clears bits 0 to 2 and leaves the remaining bits unchanged. • Test it using 0xAD as input data ARM System - On - Chip Architecture

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