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Test Results for the CT Sigma-Delta Modulator

Test Results for the CT Sigma-Delta Modulator. Yi Zhang Advisor: Prof. Gabor Temes June 6, 2014. Block Diagram. Reference switching ELD compensation [1] Multi-bit FIR Feedback. Test Setup. Die Microphotograph. Measured Output Spectrum. # of FFT: 65536 15 averages. DWA on vs. DWA off.

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Test Results for the CT Sigma-Delta Modulator

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  1. Test Results for the CT Sigma-Delta Modulator Yi Zhang Advisor: Prof. Gabor Temes June 6, 2014

  2. Block Diagram • Reference switching ELD compensation [1] • Multi-bit FIR Feedback

  3. Test Setup

  4. Die Microphotograph

  5. Measured Output Spectrum • # of FFT: 65536 • 15 averages

  6. DWA on vs. DWA off • non-linear ISI error • 1.3 dB degraded when DWA on [Karthik, 2014]

  7. Cont’d

  8. Cont’d

  9. Cont’d

  10. SNDR/SNR vs. Input Amplitude

  11. On-Chip Tuning

  12. Performance Comparison • FoMxx = Power/(2(xx-1.76)/6.02 x 2 BW) FoMSchreier = DR + 10 x log10(BW/P) [2] Mitteregger 06 [3] Dhanasekaran 09 [4] Taylor 10 [5] Shettigar 12 [6] Shu 13

  13. Test PCB Board

  14. Test Environment

  15. Reference Y. Zhang, C-H Chen, and G. Temes.: “Efficient technique for excess loop delay compensation in continuous-time ∆Σ modulators”, Electron. Lett., vol. 49, no. 24,pp. 1522-1523, 2013 G. Mitteregger, C. Ebner, S. Mechnig, T. Blon, C. Holuigue, and E. Romani, “A 14b 20mW 640MHz CMOS CT ∆Σ ADC with 20MHz Signal Bandwidth and 12b ENOB,” ISSCC Dig. Tech. Papers, pp. 131-140, Feb. 2006 V. Dhanasekaran, et al., “ A 20 MHz BW 68 dB DR CT sigma delta ADC based on a multi-bit time-domain quantizer and feedback element,” ISSCC Dig. Tech. Papers, pp. 174-175, Feb. 2009 G. Taylor and I. Galton, “ A Mostly Digital Variable-Rate Continuous Time ADC ∆Σ Modulator,” ISSCC Dig. Tech. Papers, pp. 298-299, Feb. 2010 P. Shettigar and S. Pavan, “A 15mW 3.6GS/s CT-∆Σ ADC with 36MHz Bandwidth and 83dB DR in 90nm CMOS,” ISSCC Dig. Tech. Papers, pp. 156-157, Feb. 2012. Y. Shu, J. Tsai, P. Chen, T. Lo, P. Chiu, “A 28fJ/conv-step CT ∆Σ modulator with 78dB DR and 18MHz BW in 28nm CMOS using a highly digital multibit quantizer,” ISSCC Dig. Tech. Papers, pp 268-269, Feb 2013.

  16. Thank You

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