Sassy Compiler

1. Sassy Compiler Wim Bohm Monica Chawathe Charles Ross

2. Software Architecture RCS Code Optimizations SA-C DDCF DFG AHA VHDL X86 Host Code C C Data driven Simulation PC RCS Verification Timed Simulation

3. Example • Add two images A & B • SA-C Code uint32[:] main (uint32 A[:], uint32 B[:]) { uint8 R = for a in A dot b in B { } return (array(a+b)); } return (R); • Data-flow Graph (DFG) • Token Driven Simulation • Abstract Hardware Architecture (AHA) Graph • Timed (Synchronous) Simulation • VHDL

4. DFG 1 1 0 0 ELE_GEN ELE_GEN + 1 TILE

5. AHA TKGN TKGN 1 1 CNT CNT RDWD RDWD 1 + CNT 1 BUFX WRWD

6. AHA • AHA Nodes • Clocked + Producer-Consumer State • Clocked, no state • Combinational • Sections • Producers • Clocked+State Nodes • Consumers • Clocked+State Nodes • Intermediate Nodes • Clocked, no state and combinational

7. Complex AHAs • Non-word elements • Ex: uint8 • Fifo-Unpack • Word to stream of pixels • Follows Read-Word • Window Generator • Shift Register • Width of window • Stride • 2-D Loop • One token generator per loop dimension • Innermost dimension • Calculate word address • Outer dimension • Calculate row address

8. VHDL • AHA Nodes  VHDL Component • Token-Generator Entity entity TOK_GEN is generic ( Bits : integer := 8); port ( Clock : in std_logic; Reset : in std_logic; Ready_In : out std_logic; AllReady_In : in std_logic; Data_In : in std_logic_vector(Bits-1 downto 0); Ready_Out : out std_logic; AllReady_Out : in std_logic; Data_Out : out std_logic_vector(0 downto 0)); end TOK_GEN;

9. VHDL (contd.....): Archetecture CountZero <= '1' when Count = 0 else '0'; Data_Out(0) <= CountZero and HaveVal; Ready_In <= not HaveVal; Ready_Out <= HaveVal; TProc : process (Clock, Reset) begin if Reset = '1' then Count <= (others => '0'); HaveVal <= '0'; elsif Clock'event and Clock = '1' then if AllReady_Out = '1' then Count <= Count - 1; if (CountZero = '1') then HaveVal <= '0'; end if; end if; if AllReady_In = '1' then Count <= Data_In; HaveVal <= '1'; end if; end if; end process TProc;