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Quarterly Technical Report III for Pittsburgh Digital Greenhouse

Quarterly Technical Report III for Pittsburgh Digital Greenhouse. High Speed CMOS A/D Converter Circuit for Radio Frequency Signal. Kyusun Choi. Computer Science and Engineering Department. The Pennsylvania State University. Project Goals for This Quarter.

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Quarterly Technical Report III for Pittsburgh Digital Greenhouse

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  1. Quarterly Technical Report III for Pittsburgh Digital Greenhouse High Speed CMOS A/D Converter Circuit for Radio Frequency Signal Kyusun Choi Computer Science and Engineering Department The Pennsylvania State University

  2. Project Goals for This Quarter • Design and Fab 2nd Prototype chip • Design 6 and 8 bit TIQ ADC Circuits • Design 6 and 8 bit ADC Layouts • Design 2nd Prototype Chip • Fabricate 2nd Prototype Chip

  3. Accomplished Project Milestones • Total 10 ADCs are designed (0.18um) • 6bit ADC with L=0.18um and ROM Decoder • 6bit ADC with L=0.50um and ROM Decoder • 6bit ADC with L=1.00um and ROM Decoder • 6bit ADC with L=1.00um and FAT Decoder • 6bit ADC with L=1.00um and Pipeline, ROM • 6bit ADC with L=1.00um and S&H, ROM • 8bit ADC with L=0.50um and ROM Decoder • 8bit ADC with L=1.00um and ROM Decoder • 9bit ADC with L=1.00um and ROM Decoder • 9bit ADC with L=1.50um and ROM Decoder

  4. Accomplished Project Milestones • Layout Design for 10 ADCs, Complete • 2nd Prototype Chip Design, Complete • Chip Fabrication, Submitted: • Submission date: 10/8/2001 • Vendor: MOSIS with TSMC 0.18 m foundry • Expected delivery date: December 2001

  5. 2nd Prototype Chip Summary • Die Size: 2.64mm X 2.64mm • 0.18um Digital CMOS Process • Total 56,069 Transistors • 84 Pins, 18 Power pins

  6. Chip Layout

  7. Chip Block Diagram

  8. Chip Layout Dimension

  9. Layout : 6bit, L=0.18um, ROM

  10. Layout : 6bit, L=1.00um, FAT

  11. Layout : 8bit L=0.5 um & 9bit, L=1.00um

  12. Block Diagram : 6bit ADCs ADCs

  13. Block Diagram : 8bit ADCs

  14. Block Diagram : 6bit, Pipe & S/H

  15. Block Diagram : Pads

  16. Simulation: Speed and Power • Maximum Speed • Designed with TSMC_TT parameter • With linear step from 0.5V to 1.1V • Other processes • MOSIS parameters (5) • TSMC parameters (4) • Power • Analog • Digital

  17. Simulation Results

  18. Simulation Results Worst-case delay

  19. Simulation Results • Worst-case delay (input swing: 0 V to 1.8 V) • TSMC_TT (nSec)

  20. Simulation Results • Worst-case delay (input swing: 0.5 V to 1.1 V) • TSMC_TT (nSec)

  21. Simulation Results • DNL and INL • TSMC_TT: 8bit 0.50um

  22. Simulation Results DNL and INL (LSB)

  23. Simulation Results DNL and INL (LSB)

  24. Simulation Summary • 1. High-speed with 0.18 um • Approximately50%higher speed than 0.25um • Process variation problems • 2. Power consumption • Lower power consumption • 3. Chip area • Higher circuit density

  25. URLs for The Reports • Report III • http://www.cse.psu.edu/~chip/pdg/report3.html • Slide : http://www.cse.psu.edu/~chip/pdg/p3.ppt • 2. Report II • http://www.cse.psu.edu/~chip/pdg/report2.html • Slide : http://www.cse.psu.edu/~chip/pdg/p2.ppt • 3. Report I • http://www.cse.psu.edu/~chip/pdg/rp1/report.html • Slide : http://www.cse.psu.edu/~chip/pdg/rp1/p1.ppt

  26. Publications • 1. New Paper Accepted • “Design Method and Automation of Comparator Generation for Flash A/D Converter”, • ISQED 2002 (March) • 2. Previous Paper Published • “A 1-GSPS CMOS Flash Analog-to-Digital Converter for System-on-Chip Applications”, WVLSI 2001 • “Future-Ready Ultrafast 8bit CMOS ADC for System-on–Chip Applications”, • 14th ASIC/SOC 2001

  27. CONCLUSION • Accomplished Milestones: • Total 10 ADCs Designed: 6 bit, 8 bit, and 9 bit ADCs • 2nd Prototype Chip Design • Chip Fabrication, Submitted • MOSIS 10/8/2001 • 0.18 m Digital CMOS • Return: December 2001 • Speed Increased Over 1st Proto Chip • More ADCs on 2nd Proto Chip

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