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Status and future plans for the DDL

Status and future plans for the DDL. Ervin DÉNES , Csaba SOÓS, KFKI-Research Institute for Particle Physics. Outline. DDL Current Status and Plans Radiation Tolerance Tests Results and Plans PCI-RORC (pRORC) Current Status and Plans Integration Status and Plans.

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Status and future plans for the DDL

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  1. Status and future plans for the DDL Ervin DÉNES, CsabaSOÓS, KFKI-Research Institute for Particle Physics DDL status & plans

  2. Outline • DDL • Current Status and Plans • Radiation Tolerance Tests • Results and Plans • PCI-RORC (pRORC) • Current Status and Plans • Integration • Status and Plans DDL status & plans

  3. DDL Current Status • DDL SIU and DIU prototypes • Ready for integration with detector electronics • Hardware and software tools to help the integration: • FEE simulator • API library • Web page • DDL prototypes • 1 in Bergen for TPC RCU • 1 in Turin for ITS Drift • Next: HMPID, Muon, Strips, TOF DDL status & plans

  4. DDL Plans • DDL final prototype under design • 2.5 Gb/s commodity components • Identical SIU / DIU hardware • Proposals for final DDL • DDL SIU form factor • Not on critical path for detector integration tests • Finalized after radiation tolerance tests DDL status & plans

  5. DDL Radiation Tolerance tests • TX, RX parallel interface • 8-bit data + clock • @ 106.25 MHz Coax cables Doses for 10 years Ionizing radiation: <1 krad Neutron fluences: 4x1011 n/cm2 TX interface Optical cable(loopback) S/P OT RX interface • Optical Transceiver • VCSEL, 850 nm • MM, 50/125 m • PIN fotodetector • Serial/Parallel interface • 1062.5 MHz, diff. PECL Coax cables DDL status & plans

  6. DDL Radiation Tolerance Results • PLD (Altera Flex 10K Chip, 0.35 m) • Tests (Ring oscillator frequency, Power consumption, Static RAM) • Tested up to 40 krad: no error • Gigabit Interconnect Chip (Vitesse VSC 7211, GaAs) • No errors up to 1012 n/cm2 • No errors up to 140 krad • Optical Transceiver(Agilent HFBR 5910E) • OK up to 1012 n/cm2, total of ~ 10 symbol errors • No errors up to 22.8 krad • Optical Transceiver(Infineon V23818-K305-L57) • OK up to 1012 n/cm2, total of ~ 10 symbol errors • No errors up to 28.5 krad DDL status & plans

  7. DDL Radiation Tolerance Plans • Final components and DDL SIU prototype: • Q1 ’02 • Altera PLD • ACEX (for TPC readout) (0.25 m), APEX (for DDL) (0.18 m) • Q2-Q3 ‘02 • 2.5 Gb/s electrical transceiver chip (Vitesse VSC 7146) • 2.5 Gb/s optical transceiver modules (Infineon) • Test of the complete radiation tolerant SIU • Test period up to end Oct. 2002 • Final report: 30 Nov. 2002 DDL status & plans

  8. pRORC Current Status • Prototype hardware and software available • We have 5 prototypes, 10 more delivered soon • PCI interface • PCI 32 bits 33 MHz • Use a single chip PCI interface (AMCC S5935) • Drivers for Linux Kernel 2.2x and 2.4x DDL status & plans

  9. pRORC Performance • Demonstrated with complete DDL at nominal speed • Reduced software intervention during data transfer • PCI master device transferring data into PC memory • DDL data transfer and autonomous data source at maximum PCI transfer capability • API library and test programs provided • Works with BIGPHYS or PHYSMEM memory management packages DDL status & plans

  10. pRORC performance MByte/s Block size (Bytes) DDL status & plans

  11. pRORC Plans • Faster pRORC is necessary for 2.5Gbit/s DDL • PCI 64 bits/66 MHz (528 MB/s) • Contribution to the HLT RORC prototype : • DIU interface • PCI interface with IP core DDL status & plans

  12. Integration’s Status • DDL web page for support integration • http://cern.ch/ddl • Integration with TPC-RCU is in progress • Integration with ITS Drift (CARLOS) started • Integrated with DATE V4 • Next: HMPID, Muon, Strips, TOF DDL status & plans

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