Power dissipation and propagation delay
Download
1 / 39

ECE 331 – Digital System Design - PowerPoint PPT Presentation


  • 77 Views
  • Uploaded on

Power Dissipation and Propagation Delay. ECE 331 – Digital System Design. Power Dissipation. Power Consumption. Each integrated circuit (IC) consumes power P T = P S + P D P T = total power consumed by IC P S = static or quiescent power consumption P D = dynamic power consumption.

loader
I am the owner, or an agent authorized to act on behalf of the owner, of the copyrighted work described.
capcha
Download Presentation

PowerPoint Slideshow about ' ECE 331 – Digital System Design' - maisie-cook


An Image/Link below is provided (as is) to download presentation

Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author.While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server.


- - - - - - - - - - - - - - - - - - - - - - - - - - E N D - - - - - - - - - - - - - - - - - - - - - - - - - -
Presentation Transcript
Power dissipation and propagation delay

Power Dissipation

and

Propagation Delay

ECE 331 – Digital System Design



Power consumption

ECE 331 - Digital System Design

Power Consumption

  • Each integrated circuit (IC) consumes power

  • PT = PS + PD

    • PT = total power consumed by IC

    • PS = static or quiescent power consumption

    • PD = dynamic power consumption


Static power consumption

ECE 331 - Digital System Design

Static Power Consumption

Power Dissipation


Static power consumption1

ECE 331 - Digital System Design

Static Power Consumption

  • PS = VCC * ICC

    • VCC = supply voltage

    • ICC = quiescent supply current

    • PS = static power consumption

  • ICC and VCC are specified in the datasheet for integrated circuit (IC).

  • PS for CMOS devices is very small


Example calculate the static power dissipation for a 74ls00 2 input nand gate

ECE 331 - Digital System Design

Example:

Calculate the static power dissipation for a 74LS00 2-input NAND gate.

Static Power Consumption


Example 74ls00 ttl

ECE 331 - Digital System Design

Example: 74LS00 (TTL)


Example 74ls00 ttl1

ECE 331 - Digital System Design

Example: 74LS00 (TTL)

  • Supply Voltage

    • 4.75 V <= VCC <= 5.25 V

  • Supply Current

    • High Output: ICCmax = 1.6 mA

    • Low Output: ICCmax = 4.4 mA

  • Maximum static power consumption

    • High Output: PS = 8.4 mW

    • Low Output: PS = 23.1 mW


Example 74ls00 ttl2

ECE 331 - Digital System Design

Example: 74LS00 (TTL)

  • Example: (continued)

    • Duty Cycle

      • Clock signal typically has 50% duty cycle

    • PS = PS_high * thigh + PS_low * tlow

      • PS_high = 8.4 mW

      • PS_low = 23.1 mW

      • Assume 50% duty cycle (high / low half the time)

      • PS = 8.4 mW * 0.5 + 23.1 mW * 0.5 = 15.8 mW

      • Assume 60% duty cycle (high 60% of the time)

      • PS = 8.4 mW * 0.6 + 23.1 mW * 0.4 = 14.28 mW


ECE 331 - Digital System Design

Example:

Compare the static power dissipation of the 74LS00 NAND gate with that of

the 74HC00 NAND gate.

Static Power Consumption


Example 74hc00 cmos

ECE 331 - Digital System Design

Example: 74HC00 (CMOS)


Example 74hc00 cmos1

ECE 331 - Digital System Design

Example: 74HC00 (CMOS)

  • PS = VCC * ICC

  • Supply Voltage

    • VCC = 6.0 V

  • Supply Current

    • ICC = 20 mA

  • Maximum static power consumption

    • PS = 6.0 V * 20 mA = 120 mW


Dynamic power consumption

ECE 331 - Digital System Design

Dynamic Power Consumption

Power Dissipation


Dynamic power consumption1

ECE 331 - Digital System Design

Dynamic Power Consumption

  • TTL

    • PD ~= 0 W

  • CMOS

    • PD != 0 W

    • Movement of charge into and out of device capacitances is used to determine dynamic power consumption.


Dynamic power consumption2

ECE 331 - Digital System Design

Dynamic Power Consumption

  • CMOS

    • Charge is stored in the internal (CPD) and load (CL) capacitances

      • CPD = power dissipation capacitance (internal)

      • CL = capacitance of load and wires (external)

    • Capacitances are in parallel

      • CT = total capacitance = CPD + CL

    • Stored charge (Q)

      • QT = CT * VDD = (CPD + CL) * VDD


Dynamic power consumption3

ECE 331 - Digital System Design

Dynamic Power Consumption

  • CMOS (continued)

    • Charge is moved on each output transition

      • Output transition from high to low and low to high

    • Movement of charge = current

      • IAVG = (CPD + CL) * VDD * fT

      • fT = output frequency (i.e. # of transitions per second)

    • PD = IAVG * VDD = (CPD + CL) * V2DD * fT


Example calculate the dynamic power consumption for a 74hc00 2 input nand gate

ECE 331 - Digital System Design

Example:

Calculate the dynamic power consumption for a 74HC00 2-input NAND gate.

Dynamic Power Consumption


Example 74hc00 cmos2

ECE 331 - Digital System Design

Example: 74HC00 (CMOS)


Example 74hc00 cmos3

ECE 331 - Digital System Design

Example: 74HC00 (CMOS)


Dynamic power consumption4

ECE 331 - Digital System Design

Dynamic Power Consumption

  • Example: 74HC00 (Quad 2-input NAND)

    VDD = 5 V, CPD = 22 pF, CL = 50 pF

    PD = (22 pF + 50 pF) * (5 V)2 * fT

    FT (Hz) PD

    1K 1.8 W

    1M 1.8 mW

    100M 180 mW

    IDDmax = 20 A

    PS = VDD * IDDmax = 5 V * 20 A = 100 W


Total power consumption

ECE 331 - Digital System Design

Total Power Consumption

Power Dissipation


Total power consumption1

ECE 331 - Digital System Design

Total Power Consumption

  • PT = PS + PD

  • Compare PT for Quad 2-input NAND (74xx00)

    0 Hz 1 MHz 100 MHz

    TTL 15.8 mW 15.8 mW 15.8 mW

    CMOS 100 W 1.805 mW 180 mW

  • Compare TTL and CMOS

    TTL CMOS

    PS VCC * ICC VDD * IDD

    PD ~ 0 W (CPD + CL) * V2DD * fT



Definitions

ECE 331 - Digital System Design

Definitions

  • Propagation Delay: The time from a change in one input to the final change in the output

  • Maximum Delay: Worst-case delay

  • Typical Delay: Mean delay

  • Minimum Delay: Fastest possible

  • The specifications for maximum, typical, and minimum delay are those measured by the manufacturer for the given conditions


Propagation delay

ECE 331 - Digital System Design

Propagation Delay

  • The time delay between a change in the input and the corresponding change in the output

    • tPHL = time for output to transition from high to low

    • tPLH = time for output to transition from low to high

  • Ideal Propagation Delay

input

tPHL

tPLH

output


Propagation delay1

ECE 331 - Digital System Design

V

DD

input

50%

50%

Gnd

Propagation delay

Propagation delay

V

DD

90%

90%

output

50%

50%

Gnd

10%

10%

t

t

r

f

Propagation Delay


Propagation delay2

ECE 331 - Digital System Design

Propagation Delay

  • Propagation delay is used to determine

    • When outputs are valid

    • The maximum speed of a combinational circuit

    • The maximum frequency of a sequential circuit


Simple analysis

ECE 331 - Digital System Design

Simple Analysis

  • Given: A logic circuit with multiple inputs and a single output.

  • Given: A single transition on one of the inputs.

  • Determine: The time delay to propagate the transition on the input to the output.

    • Use the propagation delay specified for each gate in the path between the input on which the transition occurred and the output.

    • The gate propagation delays are specified in the associate datasheets.


More complex analysis

ECE 331 - Digital System Design

More Complex Analysis

  • Problem: Some circuits have more than one path from an input to an output.

  • Solution:

    • Analyze every possible delay path

      or

    • Use the Worst Case Analysis

      • Provides a conservative specification

      • Often sufficient


More complex analysis1

ECE 331 - Digital System Design

More Complex Analysis

  • Problem: What if multiple inputs change at the same time?

  • Solution:

    • Analyze all combinations of input changes for all delay paths (to the output).

      or

    • Use the Worst Case Analysis


Sum of worst cases swc analysis

ECE 331 - Digital System Design

Sum of Worst Cases (SWC) Analysis

  • Write worst case delay next to each logic gate

    • Select maximum of tPLH and tPHL

  • Identify all input-output paths (i.e. all delay paths)

  • Calculate worst case delay for each path

    • Summarize in table

  • Select worst case (i.e. maximum propagation delay)


ECE 331 - Digital System Design

Example:

Determine the worst-case propagation delay using the SWC Analysis for the XOR Logic Circuit.


Example

ECE 331 - Digital System Design

Example

74F04

74LS08

74F32

f

74LS04

x

2

x

1

74F08


Example1

ECE 331 - Digital System Design

Example

74F04

74LS08

74F32

f

74LS04

x

2

x

1

TP = 32.1

74F08


Example2

ECE 331 - Digital System Design

Example

74F04

74LS08

74F32

f

74LS04

x

2

x

1

TP = 12.3

74F08


Example3

ECE 331 - Digital System Design

Example

74F04

74LS08

74F32

f

74LS04

x

2

x

1

TP = 26.1

74F08


Example4

ECE 331 - Digital System Design

Example

74F04

74LS08

74F32

f

74LS04

x

2

x

1

TP = 27.3

74F08


Example5

ECE 331 - Digital System Design

Example

Worst Case Propagation Delay = 32.1


Swc analysis summary

ECE 331 - Digital System Design

SWC Analysis - Summary

  • Permits Worst Case assessment of delay

  • Simple / Robust

  • Conservative

    • If it does not satisfy the design requirements it may be necessary to implement a more detailed analysis.

    • In particular, with the case-limiting paths


ad