4020 MMU, CAHCE & Startup.S

1. Prochip 4020 MMU, CAHCE & Startup.S 2007-12-27 4020 MMU, Cache and Startup.S

2. Prochip@ ARM720T • The ARM720T is a cached macrocell containing an ARM7TDMI core • Unified 8K write-through cache • Memory Management Unit • Write buffer • WinCE / Linux support • AMBA-compliant AHB interface • EmbeddedICE-RT • ETM Interface 4020 MMU, Cache and Startup.S 1

3. ARM Core Register File Tightly Coupled Memory L1 cache Write Buffer FIFO SRAM SDRAM Flash Hard Disk, Net Word-Word Block ARM Core Cache Memory L H Write Buffer H L Word-Word L Prochip@ Memory Hierachy 4020 MMU, Cache and Startup.S 2

4. Cache Tag Cache Tag Cache Tag Cache Tag Cache Tag Cache Tag Cache Tag V | d V | d V | d V | d V | d V | d V | d Word3 Word3 Word3 Word3 Word3 Word3 Word3 Word2 Word2 Word2 Word2 Word2 Word2 Word2 Word1 Word1 Word1 Word1 Word1 Word1 Word1 Word0 Word0 Word0 Word0 Word0 Word0 Word0 Prochip@ Cache 31 Cache Controller Cache Memory Way 1 Directory store Status Information Data section Miss Tag Field Cache Line Compare Hit 12 11 Set Index Field Data Address Bus 4 3 Data Index Field 0 Dirty bit Valid bit 4020 MMU, Cache and Startup.S 3

5. Cache Main Memory 0x0000 0x0010 0x0020 0x0030 0x0040 0x0050 address 0x0060 tag word 0x0070 index 0x0080 0x0090 tag ram 0x0064 01 00..................................01 10 00 data =  Prochip@ Cache line 4020 MMU, Cache and Startup.S 4

6. Way 0 Main Memory • Replacement Strategies: • Random • Cyclic (round robin) • Least Recently Used (LRU)† Set 0 0x0000 0x0010 0x0020 0x0030 0x0040 Way 1 0x0050 0x0060 0x0070 ? victim counter 0x0080 0x0090 2-Way, 4 Sets Way 0 Way 1 index index tag tag = = †not used in current ARM processors  data Prochip@ Cache 4020 MMU, Cache and Startup.S 4

7. 2 1 0 7 6 5 4 3 Decoder Decoder Decoder Decoder Prochip@ Cache Address Address Stored in TAG (22 bits) Index Word Unused 31 10 9 5 4 2 1 0 3 5 Cache line d0 d1 v d0 d1 Data TAG Note: Each address index maps to a single cache line which can be stored in any one of the four ways (4 way associativity) Line 0 Line 1 Line 30 Line 31 way 0 The example shown here is a 4k cache: 4 ways x 32 lines (sets) x 8 words = 4kb cache v- valid bit d0,d1 - dirty bits 4020 MMU, Cache and Startup.S 5

8. Prochip@ Memory Mangement Unit Virtual to Physical Memory mapping Memory Access Permission Cashability and Bufferability bit The Properties of MMU The C and B bits are used to control the cache and write buffer and to determine whether the access is cached or not. The access permission bits and domain are used to determine whether the access is permitted. 4020 MMU, Cache and Startup.S 6

9. Read Only • Cached • Read Only • Cached Flash Flash Flash • Read Write • Uncached • Not Buffered Peripherals Peripherals • Read Write • Cached • Buffered • Read Only • Cached SRAM SRAM SRAM Prochip@ Protection Regions Instruction Regions Memory Map Data Regions • Instruction regions must have corresponding data regions defined to allow for literal pool data access • Overlapping background region could be set Background Background 4020 MMU, Cache and Startup.S 7

10. Prochip@ Address Translation • Page tables must be stored in the level 2 memory system • MMU reads these tables and caches the results in the Translation Lookaside Buffer (TLB) • Avoids continuous memory accesses to page tables 4GB Level 2 Level 2 MMU Level 1 TLB 0MB Virtual Memory Physical Memory 4020 MMU, Cache and Startup.S 8

11. 31 20 19 12 11 10 9 8 5 4 2 1 0 IGN 00 Coarse page table base address SBZ Domain IMP 01 Section SBZ AP SBZ Domain IMP 10 C B Fine page table base address SBZ Domain IMP 11 31 16 15 12 11 10 9 8 7 6 5 4 3 2 1 0 IGN 00 Large table base address SBZ AP3 AP2 AP1 AP0 C B 01 Small table base address AP3 AP2 AP1 AP0 C B 10 Tiny table base address SBZ AP C B 11 Prochip@ Address Translation 4020 MMU, Cache and Startup.S 9

12. Prochip@ Address Translation 31 14 13 0 Translation Table Base Translation Base Translation Base SBZ Cp15 register c2 31 20 First-Level Table Index First-Level Table Index Second-Level Table Index Second-Level Table Index Page Index Page Index Virtual address Address of first level descriptor 00 Fine page table base address Fine page table base address SBZ Domain IMP First level descriptor 11 Address of second level descriptor Section 00 Tiny table base address Tiny table base address SBZ AP C B 11 Second level descriptor Physical address Tiny page translation in a fine second-level table 4020 MMU, Cache and Startup.S 10

13. Prochip@ FCSE Task A, VA 0x0 → MVA 0x00000000 → PA 0x00000000 Task B, VA 0x0 → MVA 0x04000000 → PA 0x00100000 Task C, VA 0x0 → MVA 0x08000000 → PA 0x00200000 4GB MVA MMU VA 3MB Task C 2MB Task B 32MB Task Space TLB 1MB Task A PID 0 0MB = 0 – Task A 1 – Task B 2 – Task C Virtual Memory Physical Memory 4020 MMU, Cache and Startup.S 11

14. Prochip@ Possible Booting Tasks • Handle remapping of memory at 0x0000000 from ROM to RAM • Enable branch prediction • Setup stacks • Setup TCMs • Setup Page tables & MMU • Enable MMU & Cache(s)† & TCMs • Relocate code from ROM to RAM • DCache can only operate if MMU is enabled. ICache can be enabled whenever it is deemed suitable 4020 MMU, Cache and Startup.S 11

15. Prochip@ Possible Booting Tasks 代码分析 4020 MMU, Cache and Startup.S 11