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Mixed-Signal Processing for Space Communications. by Rajan Bedi and Lewis Farrugia EADS Astrium Payload Processor Group, Mail Point C325, Gunnels Wood Road, Stevenage, Hertfordshire, SG1 2AS, England. Email: [email protected] Introduction.

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Mixed-Signal Processing for Space Communications

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Mixed signal processing for space communications l.jpg

Mixed-Signal Processing for Space Communications

by

Rajan Bedi and Lewis Farrugia

EADS Astrium

Payload Processor Group, Mail Point C325,

Gunnels Wood Road, Stevenage, Hertfordshire, SG1 2AS, England.

Email: [email protected]

Bedi


Introduction l.jpg

Introduction

  • Future low-cost, deep-space exploration missions and Earth-orbiting satellites will be made possible through the use of advanced, highly-integrated, mixed-technology microelectronics. Such systems will be built around single chip solutions using commercial foundries with special design and process enhancements for radiation hardness and extreme conditions in space.

  • EADS Astrium has started to investigate the potential advantages of extending the boundaries of the satellite digital signal processor (DSP) payload to include analogue and mixed-signal circuitry. Significant added-value may result by integrating existing on-board data processing functions with mixed-signal circuits to interface with intermediate or radio frequency (RF) carriers.

  • EADS Astrium have developed mixed-signal simulation models to enable system-level analysis and optimisation of the analogue-digital interface for satellite DSP payloads. Results have shown that the models provide accurate indication of ADC and DAC performance with different device parameters. This simulation environment is to be used as a testbed to define the specification of the next generation of mixed-signal parts to be integrated with future payloads.

Bedi


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Motivation

  • The benefits of integrating the DSP payload with mixed-signal circuits would be: lower power consumption, smaller mass, higher reliability, greater levels of reusability and improved system testing and quality – all of which contribute to the spirit of “Faster, Better, Cheaper”.

    The design of simulation models for the complete analogue processing chain, including ADCs and DACs, will allow for experimentation of device parameters in the mixed-signal interface. The results of this analysis will be used:

  • To influence the specification and sourcing of ADC/DAC devices that can be used with future DSP payloads.

  • To drive the development of a mixed-signal chip set for space communications.

  • To prevent unnecessary under-design or over-specification.

  • To establish the tolerance levels and to identify the limits to which circuit functionality and payload performance can be guaranteed in terms of ADC/DAC linearity, resolution and bandwidth.

  • To understand how non-ideal ADC/DAC devices impact the overall system error budget and how this will affect the performance of a telecommunications satellite payload.

Bedi


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Modelling ADCs and DACs

  • The specification of the ADC and DAC is key to the success of integrated wideband transceivers for space communications. Parameters such as resolution, linearity and inherent errors due to variations in the fabrication process can limit their useful dynamic range and ultimately that of a transceiver.

  • To develop accurate and reliable behavioural models for mixed-signal processing, the ADC/DAC static error sources must be modelled correctly. These ‘d.c.’ sources are: Offset Error, Gain Error, Differential Non-linearity and INL error.

  • The simulation models have been implemented using the VHDL-AMS mixed-signal hardware description language as part of a modern SOC design flow. This approach enables ADC/DAC and other intellectual property blocks to be connected directly to the DSP payload for analyses using EDA tools, e.g. high-level system verification, power consumption, speed, area and design-for-test. Mentor Graphic’s analogue and mixed-signal simulator, ADMS, allows designs to be structured using a combination of VHDL-AMS, Verilog-A, VHDL, Verilog and SPICE.

Bedi


Transfer function of a mid tread adc with offset error l.jpg

Transfer function of a mid-tread ADC with Offset Error

Bedi


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Transfer function of a DAC with Gain Error

Bedi


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The output spectrum from an ideal 12-bit ADC following single-tone testing. The measured SFDR is 92.1 dB, SINAD = 72.9 dB and dynamic range = 106 dB.

Bedi


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The output spectrum from a 12-bit ADC with added non-linearity - DNL = 0.4LSB and INL = 2.0 LSB.The measured SFDR is 72.2 dB, SINAD = 61.6 dB and dynamic range = 94.7 dB.

Bedi


The decrease in sfdr sinad and dynamic range with increasing dnl and inl constant at 2lsb l.jpg

The decrease in SFDR, SINAD and dynamic range with increasing DNL and INL constant at 2LSB.

Bedi


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The degradation in SNR with a cycle-to-cycle jitter of 5ps.Fin = 20.29453125 MHz, Ain = -1 dBFS and the measured SNR equals 59.2 dB.

Bedi


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Conclusions

  • A mixed-signal simulation environment has been developed that is to be used to investigate the potential advantages of extending the boundaries of the satellite payload DSP to include analogue and mixed-signal circuitry.

  • Simulation models allow EADS Astrium to carry out detailed analyses of ADC and DAC devices, and to predict how ADC/DAC static errors and cycle-to-cycle clock jitter/phase noise affect overall system performance.

  • The knowledge gained will assist EADS Astrium in the development and sourcing of mixed-signal devices to be used on future missions.

Bedi


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