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CISC, RISC, and Post-RISC Computers

CISC, RISC, and Post-RISC Computers. CE 140 A1/A2 4 July 2003. Required Reading. RISC vs. CISC: the Post-RISC Era John “Hannibal” Stokes http://www.arstechnica.com/cpu/4q 99/risc-cisc/rvc-1.html. Review: Basic Performance Equation. T = (N x S) / R T – program execution time

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CISC, RISC, and Post-RISC Computers

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  1. CISC, RISC, and Post-RISC Computers CE 140 A1/A2 4 July 2003

  2. Required Reading • RISC vs. CISC: the Post-RISC Era • John “Hannibal” Stokes http://www.arstechnica.com/cpu/4q 99/risc-cisc/rvc-1.html

  3. Review: Basic Performance Equation • T = (N x S) / R • T – program execution time • N – number of instructions • S – average steps per instruction • R – clock rate

  4. Technological Conditions (Late 70’s to Early 80’s) • Storage and memory • Generally, expensive and slow • Compilers • Long compilation time, unoptimized output • VLSI • “low” transistor densities

  5. Solution • Storage and memory • More compact code • Compilers • Make HLLASM translation simpler • Code in assembly for optimized program • VLSI • Reduce number of required transistors. How?

  6. “Software crisis” • Hardware costs were falling • Software development costs were rising

  7. Solution • Shift complexity from software to hardware • Bridge “semantic gap” between machine capabilities and high-level languages

  8. Complex Instruction Set Computer • Late 1970s: experimentation with complex instructions made possible by interpreter (microprogrammed control) • CISC generally required use of microprogrammed control

  9. CISC • Increased use of complex, multistep instructions • Lower N, higher S • Made the addition of new features to old microprocessors easy • Example: 8086 (1978)  Pentium (1993) by Intel

  10. CISC • Complex instructions  More steps • Larger and more expensive ICs • Sometimes lead to reduced performance • Less instructions per program  less code

  11. CISC • Powerful instructions  More direct implementation of high-level language operations • Allows more complex addressing modes

  12. CISC Issues • Larger instruction set  larger control stores  larger microprograms • Larger microprograms  slower and difficult to test • “Semantic gap”  “Semantic clash”

  13. CISC Issues • 80/20 rule – 80% of the instructions use only 20% of the instruction set • Need to maintain backward compatibility  increased development cost

  14. Reduced Instruction Set Computer • Reduced Instruction Set Computer • Mid-1970s – John Cocke – IBM 801 • 1980: Patterson and Séquin – RISC processor  SPARC • 1981: Hennessy – MIPS processor

  15. Technological Conditions • Cheaper memory • Better compilers

  16. RISC • “Make the common case fast” • Speed up 20% of instruction set • Simpler instructions • Simpler addressing modes • Increased performance • Higher N, lower S • Complexity is moved from hardware to software

  17. RISC • “Even if a RISC machine takes four or five instructions to do what a CISC machine does in one instruction, if the RISC instructions are 10 times as fast, RISC wins”

  18. RISC • Well-suited to pipelined execution, parallelism • Can be used effectively by optimizing compilers • Hardwired control  faster direct execution • Simpler hardware  Smaller chip area  more space for registers and cache

  19. RISC and Compilers • Compilers play a more prominent role • Need for intelligent, optimizing compilers

  20. RISC Design Principles • All instructions are directly executed by hardware • Hardwired Control • Maximize the rate at which instructions are issued • Instructions should be easy to decode • Regular, fixed-length instructions

  21. RISC Design Principles • Only Loads and Stores should reference memory • Provide plenty of registers

  22. CISC versus RISC • Example: • CISC: • MULT [ADDR1], [ADDR2] • RISC • LOAD A, [ADDR1] • LOAD B, [ADDR2] • MULT A, B • STORE [ADDR1], A

  23. “Why aren’t RISC machines as popular as CISC machines?” • Not a totally valid question • Big investment in software for Intel-based machines (primarily CISC) • Compatibility • Intel-based machines now have a RISC core • Common instructions  Faster • Uncommon instructions  Slower

  24. CISC and RISC • Now the term RISC refers to any computer with an ISA and CPU organization that is designed for high performance • Size of instruction set is now considered relatively unimportant • Focus on fast instructions, not number of instructions

  25. The Post-RISC Era • Current Technological Conditions • Cheap and fast memory • Better compiler features • Increased transistor count

  26. The Post-RISC Era • Performance improvements • Superscalar execution • Branch prediction • Hardware Out-of-order execution (OOO) • SIMD and FP units • Additional fast, simple instructions • Software OOO

  27. Post-RISC Processors • Intel Pentium 4 • AMD Athlon • CISC instructions translated to RISC instructions (also in the Pentium 4) • PowerPC G3 / G4 / G5 • Shows convergence of RISC and CISC with the same technologies being used

  28. Post-RISC Era • Line between CISC and RISC processors are blurred • Different problems and technological conditions  different solution, not strictly CISC or RISC • Each computer must be evaluated not just on the basis of being CISC or RISC, but as a whole, including hardware and software

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