Ece 15b computer organization spring 2011 dmitri strukov
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ECE 15B Computer Organization Spring 2011 Dmitri Strukov. Partially adapted from Computer Organization and Design, 4 th edition, Patterson and Hennessy,. Agenda. Instruction formats Addressing modes Advanced concepts. Instruction formats. Simple datapath picture.

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ECE 15B Computer Organization Spring 2011 Dmitri Strukov

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Ece 15b computer organization spring 2011 dmitri strukov

ECE 15B Computer OrganizationSpring 2011Dmitri Strukov

Partially adapted from Computer Organization and Design, 4th edition, Patterson and Hennessy,


Agenda

Agenda

  • Instruction formats

  • Addressing modes

  • Advanced concepts

ECE 15B Spring 2011


Instruction formats

Instruction formats

ECE 15B Spring 2011


Ece 15b computer organization spring 2011 dmitri strukov

Simple datapath picture

Let’s add more details on this figure to see why instruction decoding could be simple and to see what is happening with for different instructions

ECE 15B Spring 2011


Below the program

Below the Program

temp = v[k];

v[k] = v[k+1];

v[k+1] = temp;

lw $t0, 0($2)

lw $t1, 4($2)

sw $t1, 0($2)

sw $t0, 4($2)

High Level Language Program (e.g., C)

Compiler

Assembly Language Program (e.g.,MIPS)

Assembler

0000 1001 1100 0110 1010 1111 0101 1000

1010 1111 0101 1000 0000 1001 1100 0110

1100 0110 1010 1111 0101 1000 0000 1001

0101 1000 0000 1001 1100 0110 1010 1111

Machine Language Program (MIPS)

Machine Interpretation

Hardware Architecture Description (e.g., block diagrams)

Architecture Implementation

Logic Circuit Description(Circuit Schematic Diagrams)


Assembly instruction

One to one mapping

Assembly instruction

Binary code

0000 1001 1100 0110 1010 1111 0101 1000

lw $t0, 0($2)

One assembly instruction

= 32 bit vector

always 32 bits

Macro or pseudo instruction  > one line of code

Examples: shift and rotate from Quiz 1

rol $a0, $a1, $a2 subu$t0, $0, $a2

srlv$t0, $a1, $t0

sllv$a0, $a1, $a2

or $a0, $a0, $t0

ECE 15B Spring 2011


Datapath with control

Datapath With Control

ECE 15B Spring 2011


Instruction formats1

op

op

rs

rs

rt

rt

rd

constant or address

shamt

funct

6 bits

6 bits

5 bits

5 bits

5 bits

5 bits

5 bits

5 bits

16 bits

6 bits

op

address

26 bits

6 bits

Instruction formats

R-format:

I-format:

J-format:

ECE 15B Spring 2011


R format example

op

rs

rt

rd

shamt

funct

6 bits

5 bits

5 bits

5 bits

5 bits

6 bits

R-format Example

add $t0, $s1, $s2

note the order!

(green card)

special

$s1

$s2

$t0

0

add

0

17

18

8

0

32

000000

10001

10010

01000

00000

100000

000000100011001001000000001000002 = 0232402016

ECE 15B Spring 2011


R type instruction

R-Type Instruction

ECE 15B Spring 2011


Instruction formats2

op

op

rs

rs

rt

rt

rd

constant or address

shamt

funct

6 bits

6 bits

5 bits

5 bits

5 bits

5 bits

5 bits

5 bits

16 bits

6 bits

op

address

26 bits

6 bits

Instruction formats

R-format:

I-format:

J-format:

ECE 15B Spring 2011


Load instruction

Load Instruction

ECE 15B Spring 2011


Instruction formats3

op

op

rs

rs

rt

rt

rd

constant or address

shamt

funct

6 bits

6 bits

5 bits

5 bits

5 bits

5 bits

5 bits

5 bits

16 bits

6 bits

op

address

26 bits

6 bits

Instruction formats

R-format:

I-format:

J-format:

ECE 15B Spring 2011


Target addressing example

Target Addressing Example

  • Loop code from earlier example

    • Assume Loop at location 80000

ECE 15B Spring 2011


Branch on equal instruction

Branch-on-Equal Instruction

ECE 15B Spring 2011


Mips pc relative or branch addressing

op

rs

rt

constant or address

6 bits

5 bits

5 bits

16 bits

MIPS PC-relative or branch addressing

  • Branch instructions specify

    • Opcode, two registers, target address

  • Most branch targets are near branch

    • Forward or backward

  • PC-relative addressing

    • Target address = PC + offset × 4

    • PC already incremented by 4 by this time

ECE 15B Spring 2011


Instruction formats4

op

op

rs

rs

rt

rt

rd

constant or address

shamt

funct

6 bits

6 bits

5 bits

5 bits

5 bits

5 bits

5 bits

5 bits

16 bits

6 bits

op

address

26 bits

6 bits

Instruction formats

R-format:

I-format:

J-format:

ECE 15B Spring 2011


Target addressing example1

Target Addressing Example

  • Loop code from earlier example

    • Assume Loop at location 80000

ECE 15B Spring 2011


Datapath with jumps added

Datapath With Jumps Added

ECE 15B Spring 2011


Pseudodirect or jump addressing

op

address

26 bits

6 bits

Pseudodirect or Jump Addressing

  • Jump (j and jal) targets could be anywhere in text segment

    • Encode full address in instruction

  • (Pseudo)Direct jump addressing

    • Target address = PC31…28 : (address × 4)

ECE 15B Spring 2011


Implementing jumps

2

address

31:26

25:0

Implementing Jumps

Jump

  • Jump uses word address

  • Update PC with concatenation of

    • Top 4 bits of old PC

    • 26-bit jump address

    • 00

  • Need an extra control signal decoded from opcode

ECE 15B Spring 2011


Branching far away

Branching Far Away

  • If branch target is too far to encode with 16-bit offset, assembler rewrites the code

  • Example

    beq $s0,$s1, L1

    bne $s0,$s1, L2j L1L2:…

ECE 15B Spring 2011


Note on the pc incrementing

Note on the PC incrementing

  • Technical term for auto-incrementation of PC is “delayed branch”

  • By default in SPIM “delayed branch” is not checked. To see you SPIM settings look at simulator  settings

  • You can also check it by loading code to SPIM to check

    main : bne $s0, $s0, main

ECE 15B Spring 2011


Loading constant values to registers

Loading constant values to registers

  • Any immediate is 16 bit

  • To load 32 bits constant one can use addi, sll + addior better way to use

    lui rd, const(load upper immediate)

ECE 15B Spring 2011


Specific addressing mode in mips

Specific Addressing Mode in MIPS

ECE 15B Spring 2011


Various specific addressing modes in other isas

Various specific addressing modes in other ISAs

  • Absolute address

  • Immediate data

  • Inherent address

  • Register direct

  • Register indirect

  • Base register

  • Register indirect with index register

  • Register indirect with index register and displacement

  • Register indirect with index register scaled

  • Absolute address with index register

  • Memory indirect

  • Program counter relative

ECE 15B Spring 2011


Example basic x86 addressing modes

Example: Basic x86 Addressing Modes

  • Two operands per instruction

  • Memory addressing modes

    • Address in register

    • Address = Rbase + displacement

    • Address = Rbase + 2scale×Rindex (scale = 0, 1, 2, or 3)

    • Address = Rbase + 2scale×Rindex + displacement

ECE 15B Spring 2011


Advanced topics code density examples

Advanced Topics:Code density examples

ECE 15B Spring 2011


Recent study 2009

Recent study (2009)

ECE 15B Spring 2011


Code density examples

Code density examples

ECE 15B Spring 2011


Advanced topics pipelining

Advanced topics: Pipelining

ECE 15B Spring 2011


Datapath with control1

Datapath With Control

ECE 15B Spring 2011


Pipelining analogy

Pipelining Analogy

  • Pipelined laundry: overlapping execution

    • Parallelism improves performance

  • Four loads:

    • Speedup= 8/3.5 = 2.3

  • Non-stop:

    • Speedup= 2n/0.5n + 1.5 ≈ 4= number of stages

ECE 15B Spring 2011


Pipeline registers

Pipeline registers

  • Need registers between stages

    • To hold information produced in previous cycle

ECE 15B Spring 2011


Multi cycle pipeline diagram

Multi-Cycle Pipeline Diagram

  • Traditional form

ECE 15B Spring 2011


Advanced topics cache design basics

Advanced topics: Cache design basics

ECE 15B Spring 2011


Datapath with control2

Datapath With Control

ECE 15B Spring 2011


Principle of locality

Principle of Locality

  • Programs access a small proportion of their address space at any time

  • Temporal locality

    • Items accessed recently are likely to be accessed again soon

    • e.g., instructions in a loop, induction variables

  • Spatial locality

    • Items near those accessed recently are likely to be accessed soon

    • E.g., sequential instruction access, array data

ECE 15B Spring 2011


Taking advantage of locality

Taking Advantage of Locality

  • Memory hierarchy

  • Store everything on disk

  • Copy recently accessed (and nearby) items from disk to smaller DRAM memory

    • Main memory

  • Copy more recently accessed (and nearby) items from DRAM to smaller SRAM memory

    • Cache memory attached to CPU

ECE 15B Spring 2011


Direct mapped cache

Direct Mapped Cache

  • Location determined by address

  • Direct mapped: only one choice

    • (Block address) modulo (#Blocks in cache)

  • #Blocks is a power of 2

  • Use low-order address bits

ECE 15B Spring 2011


Tags and valid bits

Tags and Valid Bits

  • How do we know which particular block is stored in a cache location?

    • Store block address as well as the data

    • Actually, only need the high-order bits

    • Called the tag

  • What if there is no data in a location?

    • Valid bit: 1 = present, 0 = not present

    • Initially 0

ECE 15B Spring 2011


Example direct mapped cache

Example: Direct mapped cache

ECE 15B Spring 2011


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