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A Data Stack CoreGen

A Data Stack CoreGen. Discussion 8.1. Example of the need for a stack. A 32 x 16 Stack. A 32 x 16 Stack Module. stack_ctrl32. entity stack_ctrl is port ( clr: in STD_LOGIC; clk: in STD_LOGIC; push: in STD_LOGIC; pop: in STD_LOGIC;

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A Data Stack CoreGen

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  1. A Data StackCoreGen Discussion 8.1

  2. Example of the need for a stack

  3. A 32 x 16 Stack

  4. A 32 x 16 Stack Module

  5. stack_ctrl32 entity stack_ctrl is port ( clr: in STD_LOGIC; clk: in STD_LOGIC; push: in STD_LOGIC; pop: in STD_LOGIC; we: out STD_LOGIC; amsel: out STD_LOGIC; wr_addr: out STD_LOGIC_VECTOR (4 downto 0); rd_addr: out STD_LOGIC_VECTOR (4 downto 0); full: out STD_LOGIC; empty: out STD_LOGIC ); end stack_ctrl; 00000 wr_addr rd_addr 11111

  6. stack_ctrl32 architecture stack_ctrl_arch of stack_ctrl is signal full_flag, empty_flag: STD_LOGIC; begin stk: process(clr, clk, push, pop, full_flag, empty_flag) variable push_addr, pop_addr: STD_LOGIC_VECTOR(4 downto 0); begin if clr = '1' then push_addr := "11111"; pop_addr := "00000"; empty_flag <= '1'; full_flag <= '0'; wr_addr <= "11111"; rd_addr <= "00000"; full <= full_flag; empty <= empty_flag;

  7. 00000 wr_addr rd_addr 11111 stack_ctrl32 elsif clk'event and clk = '1' then if push = '1' then if pop =‘0' then if full_flag = '0' then push_addr := push_addr - 1; pop_addr := push_addr + 1; empty_flag <= '0'; if push_addr = "11111” then full_flag <= '1'; push_addr := "00000"; end if; end if; else –- write to top of stack (pop_addr) without pushing -- don’t change push_addr and pop_addr end if;

  8. 00000 wr_addr rd_addr 11111 stack_ctrl32 elsif pop = '1' then if empty_flag = '0' then pop_addr := pop_addr + 1; if full_flag = '0' then push_addr := push_addr + 1; end if; full_flag <= '0'; if pop_addr = "00000" then empty_flag <= '1'; end if; end if; end if; wr_addr <= push_addr; rd_addr <= pop_addr; end if;

  9. 00000 wr_addr rd_addr 11111 stack_ctrl full <= full_flag; empty <= empty_flag; if push = '1' and full_flag = '0' then we <= '1'; else we <= '0'; end if; if push = '1' and pop = ‘1' then amsel <= '1'; else amsel <= '0'; end if; end process stk; end stack_ctrl_arch;

  10. A 32 x 16 Stack Module

  11. library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; entity stack32x16 is port ( d: in STD_LOGIC_VECTOR (15 downto 0); clr: in STD_LOGIC; push: in STD_LOGIC; pop: in STD_LOGIC; clk: in STD_LOGIC; q: out STD_LOGIC_VECTOR (15 downto 0); full: out STD_LOGIC; empty: out STD_LOGIC ); end stack32x16;

  12. architecture stack32x16_arch of stack32x16 is component stack_ctrl port( clr : in std_logic; clk : in std_logic; push : in std_logic; pop : in std_logic; we : out std_logic; amsel : out std_logic; wr_addr : out std_logic_vector(4 downto 0); rd_addr : out std_logic_vector(4 downto 0); full : out std_logic; empty : out std_logic); end component;

  13. component mux2g generic( width : POSITIVE); port( a : in std_logic_vector((width-1) downto 0); b : in std_logic_vector((width-1) downto 0); sel : in std_logic; y : out std_logic_vector((width-1) downto 0)); end component; component dpram32x16 port ( A: IN std_logic_VECTOR(4 downto 0); CLK: IN std_logic; D: IN std_logic_VECTOR(15 downto 0); WE: IN std_logic; DPRA: IN std_logic_VECTOR(4 downto 0); DPO: OUT std_logic_VECTOR(15 downto 0); SPO: OUT std_logic_VECTOR(15 downto 0)); end component;

  14. signal wr_addr, rd_addr : std_logic_vector(4 DOWNTO 0); signal wr2_addr, rd2_addr: std_logic_vector(4 DOWNTO 0); signal we, amsel: std_logic; constant bus_width: integer := 5; begin mem1 : dpram32x16 port map ( A => wr2_addr, CLK => clk, D => d, WE => we, DPRA => rd_addr, DPO => q, SPO => open);

  15. mux2: mux2g generic map(width => bus_width) port map (a => wr_addr,b => rd_addr, sel => amsel, y => wr2_addr); sa1: stack_ctrl port map (clr => clr, clk => clk, push => push, pop => pop, we => we, wr_addr => wr_addr, rd_addr => rd_addr, full => full, empty => empty, amsel => amsel); end stack32x16_arch;

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