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Low Cost DAQ Implementation . Written by: Gabriel Heifets Alexander Zaprudsky Instructor: Evgeniy Kuksin. Project Goal. Build a complete multipurpose DAQ: Find the best price/performance in class components . Create schematics design. Design PCB layout and produce it.

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slide1

Low Cost DAQ

Implementation

  • Written by: Gabriel Heifets
        • Alexander Zaprudsky
  • Instructor: EvgeniyKuksin
project goal
Project Goal

Build a complete multipurpose DAQ:

  • Find the best price/performance in class components.
  • Create schematics design.
  • Design PCB layout and produce it.
analog inputs
Analog inputs

Analog Input requirements:

  • 8 independent channels.
  • +/- 10v Input Range.
  • At least 1MOhm Input impedance.
  • BW>100khz.
analog inputs voltage input range problem
Analog inputs Voltage input range problem

The issue is that we want to sample +/- 10 volt with our DAQ system, but the internalMSP430 ADC is capable to handle 0~3 voltage. To achieve our goal, three possible solutions were tested.

analog inputs voltage input range problem1
Analog inputs Voltage input range problem

Method 1:

The first solution was to interface each ADC channel to a PGA AD8250, which is capable to handle +/- 13.5 volt, and reduce it to an ADC valid voltage.

+ 3V

Reduced

Analog

Inputs

PGA AD8250

MUX

ADC

+/- 10V

Analog

Inputs

+/- 10v power source

analog inputs voltage input range problem2
Analog inputs Voltage input range problem

Method 1:

Advantages:

1: No voltage translation is needed, PGA is capable to handle up to +/- 13.5 volt

2. Rin > 1Gohm

3. Cin < 0.5pF

analog inputs voltage input range problem3
Analog inputs Voltage input range problem

Method 1:

Disadvantages:

1: One input PGA, we will have to use 8 of it’s kind, or a MUX.

2: A high BOM and volume price (AD8250 = 5$)

3: An additional power solution for the PGA’s power demands: +/-15 volts

analog inputs voltage input range problem4
Analog inputs Voltage input range problem

Method 2:

Each ADC input is interfaced to a simple OpAmp with a constant gain with a low offset voltage. Three OpAmp were compared: OPA4188, AD8624, LTC1151

analog inputs voltage input range problem5
Analog inputs Voltage input range problem

OPA4188

ADC

+/- 10V

Analog

Inputs

+ 3VReduced

Analog Inputs

OPA4188

+/- 10v power source

analog inputs voltage input range problem6
Analog inputs Voltage input range problem

Method 2:

Advantages:

1: BOM price is lower then in Method 1

2. Rin > 100MOhm

3. Cin < 6pF

analog inputs voltage input range problem7
Analog inputs Voltage input range problem

Method 2:

Disadvantages:

1: One 4 inputs OpAmps, we will have to use 2 of it’s kind.

2: OpAms with a low offset voltage are expensive.

(5.88 $, 7.12$, 23.2$ accordingly)

3: An additional power solution for the OpAmps power demands: +/-10 volts

4: OpAmps have a constant gain.

analog inputs voltage input range problem8
Analog inputs Voltage input range problem

Method 3:

An analog inputs are interfaced to an 8 inputs PGA116. The PGA’s valid voltage levels are 0~4, so a voltage dividers (implemented with low tolerance resistors and reference voltage) will be added to the PGA’s inputs.

Vref

3v – 0v

Reduced

Analog

Inputs

ADC

Voltage

Dividers

PGA 116

+/- 10v

Analog

Inputs

analog inputs voltage input range problem9
Analog inputs Voltage input range problem

Method 3:

Advantages

1: Low BOM price: only one PGA is needed for an 8 inputs. The PGA’s price is relatively low, PGA116 = 2.25$.

2. Supply voltage: 4V, no comprehensive power solution is needed.

3. Programmable output gain.

analog inputs voltage input range problem10
Analog inputs Voltage input range problem

Method 3:

Disadvantages:

1: Low PGA’s inputs voltage range tolerance – additional voltage translator required.

2: Low input impedance of the complete circuit.

analog outputs
Analog Outputs

Analog Output requirements:

  • 4 independent channels.
  • +/- 10v capable outputs.
  • Iout Current > 5mA per output.
  • 12bit Resolution.
  • BW>1kHz
  • Internal flash or E2PROM for values retention.

(Optional)

analog outputs analog voltage generation1
Analog Outputs Analog Voltage Generation

Analog voltage generation is implemented with an MCP4728 DAC. This DAC choice among the other DACs will be featured in upcoming table. To extend the output voltage range to +/-10V, an optional amplifier circuit (based on an LM2903), was added.

analog outputs choosing dac
Analog Outputs Choosing DAC

Depending on the parameters benefit, and it’s low cost, MCP4728 DAC was chosen.

analog outputs analog voltage generation2
Analog Outputs Analog Voltage Generation

The MCP4728 DAC voltage outputs are controlled through I2C interface. To reduce the over analog voltage outputs BOM price, the MCP4728 IC was chosen although it’s lower accuracy. To compensate this disadvantage, a feedback calibration circuit implemented.

analog outputs analog voltage calibration
Analog Outputs Analog Voltage Calibration

Two calibration method were considered and BOM optimized:

1: The four voltage outputs are introduced to a four channel MUX, and the MUX output divided by a high precision resistors to accommodate MSP430 valid voltage level.

Total BOM price for this method: 0.172$+2.8$=2.872$

analog outputs voltage calibration
Analog Outputs Voltage Calibration

2: Each one of the four channels will be divided by a high precision resistors to an MSP430 valid input voltage.

Total BOM price for this method: 0.688$

During to lower BOM price, the second method was implemented in our solution.

slide24
PWM

PWM requirements:

  • opticaly isolated OD/OC.
  • Isink> 2A.
  • Vmax > 48v.
slide26
PWM

PWM outputs are generated by MSP430, and optically isolated by an optic solid state relay VO14642AT. To drive the VO14642AT inner LED MOSFET driver was added.

slide27
GPIO

GPIO requirements:

  • 8 GPIO channels.
  • 5V TTL levels.
  • Drive capability of 5mA.
slide29
GPIO

A two methods were exanimated to implement the GPIOs level translation.

1: A dedicated solution by a level translators that are available on the market

2: Single MOSFET based voltage translation for an each GPIO.

During the BOM consideration, METHOD 2 was chosen.

power management
Power Management

Power requirements:

  • High accuracy Vref to achieve +/- 2 LSB in ADC sampling accuracy.
  • LDOs for power supplies.
  • Step up converter to +10v for the OpAmp supply to achieve analog outputs +10v requirement (Optional).
power management external vref
Power ManagementExternal Vref

We need accuracy of +/- 2 LSB with 12bit ADC i.e.

The accuracy of the ADC sampling depends of +/- Vref:

power managment external vref
Power ManagmentExternal Vref

The MSP430F5529 has an internal Vref with accuracy of:

But in order to achieve accuracy of +/- 2 LBS the accuracy of the Vref should be at least 0.1%.

So the LM4132BMF an external Vref with accuracy of 0.1% was chosen.

power management stepup converter
Power ManagementStepUp Converter

In order to get +10v from +5v USB power for the optional OpAmp power supply in the Analog Outputs circuit we decided to use charge pumps instead of Boost converter to prevent possible noises and to reduce BOM price.

Because we can’t trust that the USB power is always +5v and not less, we couldn’t use only one charge pump to double it, so we needed two charge pumps with more than +5v operating voltage range. We found only one charge pump with such operating voltage range - ICL7660S

power management ldo
Power ManagementLDO

In order to supply stable power of 3.3v and 4.5v to the components we used TLV70233DBVR and

TLV70245DBV accordingly because of they relatively low price – 0.16$ for each.

making pcb layout
Making PCB layout

PCB design software:

  • OrcadAlegro PCB Editor

Components library:

  • A standard HSDSL footprints library
making pcb layout1
Making PCB layout

Layers:

  • The PCB contains four layers. The top layer is dedicated to a components’ placement and a signal routing.
  • The second layer dedicated to the powers’ planes
  • The third layer dedicated to the ground plane
  • The bottom layer dedicated to the signals routing
making pcb layout2
Making PCB layout

Signal types:

  • One differential pair. This pair used for an USB communication, and demands 90ohm impedance. The PCB manufacturer will have to make the desired calculations according to the applied material.
  • Power signals: all power signals, except the planes, where routed with a traces at least 20 mil width.
making pcb layout3
Making PCB layout

High noising components:

Switching components that are implements our charge pump, were placed in an isolated part of the PCB, and surrounded with a grounded shield.

making pcb layout4
Making PCB layout

High noising components:

Analog and Digital signals and Power supplies are separated one from another to prevent parasitic leakage and crosstalk to achieve a better accuracy.

making pcb layout5
Making PCB layout

USB differential 90ohm pair:

To calculate the width of the USB data traces the following equation was used:

Where:

Z=45ohm (desired impedance)

Er=4 (PCB dielectric –layer C)

H=5 (dielectric thickness between the pair layer (A) and a power plane (D) )

T= 1.4 (thickness of copper traces)

W= 9.5 The calculated traces width

making pcb layout6
Making PCB layout

High accurate components:

  • The vref generator that is dedicated for the calibration purposes is placed as close as possible to the vref sense point to prevent additional noises.
  • Vref routing was implemented a stardesign and not as a daisy chain.
making pcb layout7
Making PCB layout

Free PCB areas:

All the PCB areas that are left free from the routing traces were filled with a solid ground planes to make better EMIprotection. A dozen of VIAs were added to provide better connection between the ground planes, and to make the current return path as short as possible.

making pcb layout8
Making PCB layout

PCB housekeeping:

All island that were created during solid planes adding where detected and cleared. One way planes and traces that are formed so called “antennas” were eliminated or grounded.

optional features
Optional features

1. Firmware upgrade over USB channel (Using TI BSL feature).

2. Making traces width to match the component’s pin’s footprint width or wider – to reduce ESR.

3. Adding maximal quantity of solid ground traces to the decoupling capacitors (trace to each side of the capacitor pin’s footprint) – to reduce impedance by paralleling traces.

4. Using an arc instead of sharp angles on a trace turns to reduce signal reflections

5. Adding “tear drops” on every connector pins

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