Logic design fundamentals 2
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Logic Design Fundamentals - 2. Lecture L1.2. Logic Design Fundamentals - 2. Basic Gates Basic Combinational Circuits Basic Sequential Circuits. Basic Combinational Circuits. Multiplexers 7-Segment Decoder Comparators Decoders Adders Shifters Code Converters

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Logic design fundamentals 2

Logic Design Fundamentals - 2

Lecture L1.2


Logic design fundamentals 21

Logic Design Fundamentals - 2

  • Basic Gates

  • Basic Combinational Circuits

  • Basic Sequential Circuits


Basic combinational circuits

Basic Combinational Circuits

  • Multiplexers

  • 7-Segment Decoder

  • Comparators

  • Decoders

  • Adders

  • Shifters

  • Code Converters

  • Arithmetic Logic Units

  • ROM


Combinational logic

Combinational

Logic

inputs

outputs

Combinational Logic

Outputs depend only on the current inputs


Multiplexers

Multiplexers

A multiplexer is a digital switch

MUX

1 output, Z = X(s)

2n inputs

X(0, 2n -1)

n control lines

s( 0, n-1)


Multiplexers1

4 x 1

MUX

s1

s0

Y

0 0 C0

0 1 C1

1 0 C2

1 1 C3

Multiplexers

C0

C1

Y

C2

C3

s1

s0


Multiplexers2

4 x 1

MUX

Multiplexers

s1

s0

Y

C0

0 0 C0

0 1 C1

1 0 C2

1 1 C3

C1

Y

C2

C3

s1

s0

A multiplexer is a

digital switch

0 0


Multiplexers3

4 x 1

MUX

Multiplexers

s1

s0

Y

C0

0 0 C0

0 1 C1

1 0 C2

1 1 C3

C1

Y

C2

C3

s1

s0

0 1


Multiplexers4

4 x 1

MUX

Multiplexers

s1

s0

Y

C0

0 0 C0

0 1 C1

1 0 C2

1 1 C3

C1

Y

C2

C3

s1

s0

1 0


Multiplexers5

4 x 1

MUX

Multiplexers

s1

s0

Y

C0

0 0 C0

0 1 C1

1 0 C2

1 1 C3

C1

Y

C2

C3

s1

s0

1 1


A 2 x 1 mux

A 2 x 1 MUX

Behavior

if (s0 = '0') then

Z := A;

else

Z := B;

end if;


A 4 x 1 mux

if (s0 = '0') then

A := C0;

B := C2;

else

A := C1;

B := C3;

end if;

A 4 x 1 MUX

if (s1 = '0') then

if (s0 = '0') then

Z := C0;

else

Z := C1;

end if;

else

if (s0 = '0') then

Z := C2;

else

Z := C3;

end if;

end if;

if (s1 = '0') then

Z := A;

else

Z := B;

end if;


A 4 x 1 mux1

A 4 x 1 MUX

case s is

when "00" => Z <= C0;

when "01" => Z <= C1;

when "10" => Z <= C2;

when others => Z <= C3;

end case;


N line 2 to 1 multiplexer

n-line 2-to-1 Multiplexer

n-line

2 x 1 MUX

a(n-1:0)

y(n-1:0)

b(n-1:0)

sel y

0 a

1 b

sel


An n line 2 x 1 mux

a(n-1:0)

n-line

2 x 1

y(n-1:0)

MUX

b(n-1:0)

sel

An n-line 2 x 1 MUX

library IEEE;

use IEEE.std_logic_1164.all;

entity mux2g is

generic (width:positive);

port (

a: in STD_LOGIC_VECTOR(width-1 downto 0);

b: in STD_LOGIC_VECTOR(width-1 downto 0);

sel: in STD_LOGIC;

y: out STD_LOGIC_VECTOR(width-1 downto 0)

);

end mux2g;


Entity

generic statement defines

width of bus

Entity

Each entity must begin with these library and use statements

library IEEE;

use IEEE.std_logic_1164.all;

entity mux2g is

generic (width:positive);

port (

a: in STD_LOGIC_VECTOR(width-1 downto 0);

b: in STD_LOGIC_VECTOR(width-1 downto 0);

sel: in STD_LOGIC;

y: out STD_LOGIC_VECTOR(width-1 downto 0)

);

end mux2g;

port statement defines inputs and outputs


Entity1

Entity

Mode: in or out

library IEEE;

use IEEE.std_logic_1164.all;

entity mux2g is

generic (width:positive);

port (

a: in STD_LOGIC_VECTOR(width-1 downto 0);

b: in STD_LOGIC_VECTOR(width-1 downto 0);

sel: in STD_LOGIC;

y: out STD_LOGIC_VECTOR(width-1 downto 0)

);

end mux2g;

Data type: STD_LOGIC,

STD_LOGIC_VECTOR(width-1 downto 0);


Standard logic

Standard Logic

library IEEE;

use IEEE.std_logic_1164.all;

type std_ulogic is (‘U’, -- Uninitialized

‘X’ -- Forcing unknown

‘0’ -- Forcing zero

‘1’ -- Forcing one

‘Z’ -- High impedance

‘W’ -- Weak unknown

‘L’ -- Weak zero

‘H’ -- Weak one

‘-’); -- Don’t care


Standard logic1

Standard Logic

Type std_ulogic is unresolved.

Resolved signals provide a mechanism

for handling the problem of multiple

output signals connected to one signal.

subtype std_logic is resolved std_ulogic;


Logic design fundamentals 2

a(n-1:0)

n-line

2 x 1

y(n-1:0)

MUX

b(n-1:0)

sel

Architecture

architecture mux2g_arch of mux2g is

begin

mux2_1: process(a, b, sel)

begin

if sel = '0' then

y <= a;

else

y <= b;

endif;

end process mux2_1;

end mux2g_arch;

Note: <= is signal assignment


Logic design fundamentals 2

Architecture

entity name

process sensitivity list

architecture mux2g_arch of mux2g is

begin

mux2_1: process(a, b, sel)

begin

if sel = '0' then

y <= a;

else

y <= b;

endif;

end process mux2_1;

end mux2g_arch;

Sequential statements (if…then…else) must be in a process

Note begin…end

in process

Note begin…end

in architecture


An n line 4 x 1 multiplexer

Sely

“00”a

“01”b

“10”c

“11”d

An n-line 4 x 1 multiplexer

a(n-1:0)

8-line

b(n-1 :0)

4 x 1

y(n-1 :0)

c(n-1 :0)

MUX

d(n-1 :0)

sel(1:0)


An 8 line 4 x 1 multiplexer

An 8-line 4 x 1 multiplexer

library IEEE;

use IEEE.std_logic_1164.all;

entity mux4g is

generic(width:positive := 8);

port (

a: in STD_LOGIC_VECTOR (width-1 downto 0);

b: in STD_LOGIC_VECTOR (width-1 downto 0);

c: in STD_LOGIC_VECTOR (width-1 downto 0);

d: in STD_LOGIC_VECTOR (width-1 downto 0);

sel: in STD_LOGIC_VECTOR (1 downto 0);

y: out STD_LOGIC_VECTOR (width-1 downto 0)

);

end mux4g;


Example of case statement

Sely

“00”a

“01”b

“10”c

“11”d

Example of case statement

architecture mux4g_arch of mux4g is

begin

process (sel, a, b, c, d)

begin

case sel is

when "00" => y <= a;

when "01" => y <= b;

when "10" => y <= c;

when others => y <= d;

end case;

end process;

end mux4g_arch;

Note implies operator =>

Must include ALL possibilities

in case statement


7 segment display

7-Segment Display

seg7dec

D(3:0)

AtoG(6:0)

Truth table

D a b c d e f g

8 1 1 1 1 1 1 1

9 1 1 1 1 0 1 1

A 1 1 1 0 1 1 1

b 0 0 1 1 1 1 1

C 1 0 0 1 1 1 0

d 0 1 1 1 1 0 1

E 1 0 0 1 1 1 1

F 1 0 0 0 1 1 1

D a b c d e f g

0 1 1 1 1 1 1 0

1 0 1 1 0 0 0 0

2 1 1 0 1 1 0 1

3 1 1 1 1 0 0 1

4 0 1 1 0 0 1 1

5 1 0 1 1 0 1 1

6 1 0 1 1 1 1 1

7 1 1 1 0 0 0 0


Logic design fundamentals 2

7-Segment Display

Verilog

case(D)

0: AtoG = 7'b1111110;

1: AtoG = 7'b0110000;

2: AtoG = 7'b1101101;

3: AtoG = 7'b1111001;

4: AtoG = 7'b0110011;

5: AtoG = 7'b1011011;

6: AtoG = 7'b1011111;

7: AtoG = 7'b1110000;

8: AtoG = 7'b1111111;

9: AtoG = 7'b1111011;

'hA: AtoG = 7'b1110111;

'hb: AtoG = 7'b0011111;

'hC: AtoG = 7'b1001110;

'hd: AtoG = 7'b0111101;

'hE: AtoG = 7'b1001111;

'hF: AtoG = 7'b1000111;

default: AtoG = 7'b1111110; // 0

endcase

Behavior

seg7dec

D(3:0)

AtoG(6:0)


Logic design fundamentals 2

7-Segment Display

VHDL

-- seg7dec

with digit select

ssg <="1001111" when "0001",--1

"0010010" when "0010",--2

"0000110" when "0011",--3

"1001100" when "0100",--4

"0100100" when "0101",--5

"0100000" when "0110",--6

"0001111" when "0111",--7

"0000000" when "1000",--8

"0000100" when "1001",--9

"0001000" when "1010",--A

"1100000" when "1011",--b

"0110001" when "1100",--C

"1000010" when "1101",--d

"0110000" when "1110",--E

"0111000" when "1111",--F

"0000001" when others;--0

Behavior

(Active LOW)

AtoG

seg7dec

digit(3:0)

sseg(6:0)


Comparators

Comparators

Recall that an XNOR gate can

be used as an equality detector

XNOR

X

if X = Y then

Z <= '1';

else

Z <= '0';

end if;

Z

Y

Z = !(X $ Y)

Z = X xnor Y

Z = ~(X @ Y)

X Y Z

0 0 1

0 1 0

1 0 0

1 1 1


4 bit equality comparator

4-Bit Equality Comparator

A: in STD_LOGIC_VECTOR(3 downto 0);

B: in STD_LOGIC_VECTOR(3 downto 0);

A_EQ_B: out STD_LOGIC;


Logic design fundamentals 2

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity eqdet4 is

Port ( A : in std_logic_vector(3 downto 0);

B : in std_logic_vector(3 downto 0);

A_EQ_B : out std_logic);

end eqdet4;

architecture Behavioral of eqdet4 is

signal C: std_logic_vector(3 downto 0);

begin

C <= A xnor B;

A_EQ_B <= C0 and C1 and C2 and C3;

end Behavioral;


Comparators1

comp

A_EQ_B

A(n-1:0)

A_GT_B

A_LT_B

B(n-1:0)

A_UGT_B

A_ULT_B

Comparators

A, B

signed

A, B

unsigned

Signed: 2's complement signed numbers


Logic design fundamentals 2

-- Comparator for unsigned and signed numbers

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_arith.all;

use IEEE.std_logic_unsigned.all;

entity comp is

generic(width:positive);

port (

A: in STD_LOGIC_VECTOR(width-1 downto 0);

B: in STD_LOGIC_VECTOR(width-1 downto 0);

A_EQ_B: out STD_LOGIC;

A_GT_B: out STD_LOGIC;

A_LT_B: out STD_LOGIC;

A_ULT_B: out STD_LOGIC;

A_UGT_B: out STD_LOGIC

);

end comp;

comp

A_EQ_B

A(n-1:0)

A_GT_B

A_LT_B

B(n-1:0)

A_UGT_B

A_ULT_B


Logic design fundamentals 2

architecture comp_arch of comp is

begin

CMP: process(A,B)

variable AVS, BVS: signed(width-1 downto 0);

begin

for i in 0 to width-1 loop

AVS(i) := A(i);

BVS(i) := B(i);

end loop;

A_EQ_B <= '0';

A_GT_B <= '0';

A_LT_B <= '0';

A_ULT_B <= '0';

A_UGT_B <= '0';

if (A = B) then

A_EQ_B <= '1';

end if;

if (AVS > BVS) then

A_GT_B <= '1';

end if;

if (AVS < BVS) then

A_LT_B <= '1';

end if;

if (A > B) then

A_UGT_B <= '1';

end if;

if (A < B) then

A_ULT_B <= '1';

end if;

end process CMP;

end comp_arch;

comp

A_EQ_B

A(n-1:0)

A_GT_B

A_LT_B

B(n-1:0)

A_UGT_B

A_ULT_B

Note: All outputs must be

assigned some value.

The last signal assignment

in a process is the value assigned


Logic design fundamentals 2

4-Bit Comparator


Full adder

Full Adder

Truth table

Ci

Si

Ai

Ci+1

Bi

Behavior

Ci+1:Si = Ci + Ai + Bi


Full adder1

Full Adder

Block Diagram


4 bit adder

4-Bit Adder

C 1 1 1 0

0:A 0 1 1 0 1

0:B 0 0 1 1 1

C4:S 1 0 1 0 0


Logic design fundamentals 2

library IEEE;

use IEEE.STD_LOGIC_1164.all;

use IEEE.STD_LOGIC_unsigned.all;

entity adder4 is

port(

A : in STD_LOGIC_VECTOR(3 downto 0);

B : in STD_LOGIC_VECTOR(3 downto 0);

carry : out STD_LOGIC;

S : out STD_LOGIC_VECTOR(3 downto 0)

);

end adder4;

architecture adder4 of adder4 is

begin

process(A,B)

variable temp: STD_LOGIC_VECTOR(4 downto 0);

begin

temp := ('0' & A) + ('0' & B);

S <= temp(3 downto 0);

carry <= temp(4);

end process;

end adder4;


Logic design fundamentals 2

4-Bit Adder


Logic design fundamentals 2

3-to-8 Decoder

A: in STD_LOGIC_VECTOR(2 downto 0);

Y: out STD_LOGIC_VECTOR(0 to 7);

Behavior

for i in 0 to 7 loop

if(i = conv_integer(A)) then

Y(i) <= ‘1’;

else

Y(i) <= ‘0’;

end if;

end loop;


Logic design fundamentals 2

library IEEE;

use IEEE.STD_LOGIC_1164.all;

use IEEE.STD_LOGIC_arith.all;

use IEEE.STD_LOGIC_unsigned.all;

entity decode38 is

port(

A : in STD_LOGIC_VECTOR(2 downto 0);

Y : out STD_LOGIC_VECTOR(0 to 7)

);

end decode38;

architecture decode38 of decode38 is

begin

process(A)

variable j: integer;

begin

j := conv_integer(A);

for i in 0 to 7 loop

if(i = j) then

Y(i) <= '1';

else

Y(i) <= '0';

end if;

end loop;

end process;

end decode38;

3-to-8 Decoder


Logic design fundamentals 2

3-to-8 Decoder


Shifters

Shifters

Shift right

Shift left

Arithmetic shift right


Logic design fundamentals 2

shift4.vhd

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_unsigned.all;

entity shifter is

generic(width:positive := 4);

port (

D: in STD_LOGIC_VECTOR(width-1 downto 0);

s: in STD_LOGIC_VECTOR(1 downto 0);

Y: out STD_LOGIC_VECTOR(width-1 downto 0)

);

end shifter;


Logic design fundamentals 2

architecture shifter_arch of shifter is

begin

shift_1: process(D, s)

begin

case s is

when "00" =>-- no shift

Y <= D;

when "01" =>-- U2/

Y <= '0' & D(width-1 downto 1);

when "10" =>-- 2*

Y <= D(width-2 downto 0) & '0';

when "11" =>-- 2/

Y <= D(width-1) & D(width-1 downto 1);

whenothers =>-- no shift

Y <= D;

end case;

end process shift_1;

end shifter_arch;


Code converters

Code Converters

  • Gray Code Converter

  • Binary-to-BCD Converter


Gray code

Gray Code

Definition: An ordering of 2n binary numbers such that

only one bit changes from one entry to the next.

Binary coding {0...7}: {000, 001, 010, 011, 100, 101, 110, 111}

Gray coding {0...7}: {000, 001, 011, 010, 110, 111, 101, 100}

Not unique

One method for generating a Gray code sequence:

Start with all bits zero and successively flip the right-most bit that produces a new string.


Logic design fundamentals 2

Binary - Gray Code Conversions

Gray code: G(i), i = n – 1 downto 0

Binary code: B(i), i = n – 1 downto 0

Binary coding {0...7}: {000, 001, 010, 011, 100, 101, 110, 111}

Gray coding {0...7}: {000, 001, 011, 010, 110, 111, 101, 100}

Convert Binary to Gray:

Copy the most significant bit.

For each smaller i

G(i) = B(i+1) xor B(i)

Convert Gray to Binary:

Copy the most significant bit.

For each smaller i

B(i) = B(i+1) xor G(i)


Logic design fundamentals 2

bin2gray.vhd

library IEEE;

use IEEE.STD_LOGIC_1164.all;

entity bin2gray is

generic(width:positive := 3);

port(

B : in STD_LOGIC_VECTOR(width-1 downto 0);

G : out STD_LOGIC_VECTOR(width-1 downto 0)

);

end bin2gray;

architecture bin2gray of bin2gray is

begin

process(B)

begin

G(width-1) <= B(width-1);

for i in width-2 downto 0 loop

G(i) <= B(i+1) xor B(i);

end loop;

end process;

end bin2gray;


Logic design fundamentals 2

Binary to Gray Code Conversion


Logic design fundamentals 2

library IEEE;

use IEEE.STD_LOGIC_1164.all;

entity gray2bin is

generic(width:positive := 3);

port(

G : in STD_LOGIC_VECTOR(width-1 downto 0);

B : out STD_LOGIC_VECTOR(width-1 downto 0)

);

end gray2bin;

architecture gray2bin of gray2bin is

begin

process(G)

variable BV: STD_LOGIC_VECTOR(width-1 downto 0);

begin

BV(width-1) := G(width-1);

for i in width-2 downto 0 loop

BV(i) := BV(i+1) xor G(i);

end loop;

B <= BV;

end process;

end gray2bin;

gray2bin.vhd


Logic design fundamentals 2

Gray Code to Binary Conversion


Binary to bcd conversion

Binary-to-BCD Conversion

  • Shift and add 3 algorithm

  • RTL solution

  • Behavioral solution


Shift and add 3 algorithm

Shift and Add-3 Algorithm

11. Shift the binary number left one bit.

22. If 8 shifts have taken place, the BCD number is in the

Hundreds, Tens, and Units column.

33. If the binary value in any of the BCD columns is 5 or greater,

add 3 to that value in that BCD column.

44. Go to 1.


Logic design fundamentals 2

Steps to convert an 8-bit binary number to BCD


Truth table for add 3 module

Truth table for Add-3 Module

A3 A2 A1 A0

C

S3 S2 S1 S0


Logic design fundamentals 2

Binary-to-BCD

Converter

RTL Solution


Logic design fundamentals 2

Binary-to-BCD Converter: Behavioral Solution

-- Title: Binary-to-BCD Converter

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_unsigned.all;

entity binbcd is

port (

B: in STD_LOGIC_VECTOR (7 downto 0);

P: out STD_LOGIC_VECTOR (9 downto 0)

);

end binbcd;


Logic design fundamentals 2

architecture binbcd_arch of binbcd is

begin

bcd1: process(B)

variable z: STD_LOGIC_VECTOR (17 downto 0);

begin

for i in 0 to 17 loop

z(i) := '0';

end loop;

z(10 downto 3) := B;

for i in 0 to 4 loop

if z(11 downto 8) > 4 then

z(11 downto 8) := z(11 downto 8) + 3;

end if;

if z(15 downto 12) > 4 then

z(15 downto 12) := z(15 downto 12) + 3;

end if;

z(17 downto 1) := z(16 downto 0);

end loop;

P <= z(17 downto 8);

end process bcd1;

end binbcd_arch;


Logic design fundamentals 2

16-bit

Binary-to-BCD

Converter


Logic design fundamentals 2

Verilog binbcd

module binbcd(B,P);

input [15:0] B;

output [15:0] P;

reg [15:0] P;

reg [31:0] z;

integer i;


Logic design fundamentals 2

always @(B)

begin

for(i = 0; i <= 31; i = i+1)

z[i] = 0;

z[18:3] = B;

for(i = 0; i <= 12; i = i+1)

begin

if(z[19:16] > 4)

z[19:16] = z[19:16] + 3;

if(z[23:20] > 4)

z[23:20] = z[23:20] + 3;

if(z[27:24] > 4)

z[27:24] = z[27:24] + 3;

if(z[31:28] > 4)

z[31:28] = z[31:28] + 3;

z[31:1] = z[30:0];

end

P = z[31:16];

end

endmodule


Arithmetic logic units

Arithmetic Logic Units

  • ALU1

    • Shifting, Increment and Decrement Instructions

  • ALU2

    • Arithmetic and Logic Instructions

  • ALU3

    • Comparators


Logic design fundamentals 2

ALU1

Shifting, Increment and Decrement Instructions


Logic design fundamentals 2

alu1.vhd

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_unsigned.all;

entity alu1 is

generic(width:positive);

port (

a: in STD_LOGIC_VECTOR(width-1 downto 0);

sel: in STD_LOGIC_VECTOR(2 downto 0);

y: out STD_LOGIC_VECTOR(width-1 downto 0)

);

end alu1;


Logic design fundamentals 2

architecture alu1_arch of alu1 is

begin

alu_1: process(a, sel)

variable true, false: STD_LOGIC_VECTOR (width-1 downto 0);

begin

-- true is all ones; false is all zeros

for i in 0 to width-1 loop

true(i) := '1';

false(i) := '0';

end loop;

case sel is

when "000" =>-- 1+

y <= a + 1;

when "001" =>-- 1-

y <= a - 1;

when "010" =>-- invert

y <= not a;

when "011" =>-- 2*

y <= a(width-2 downto 0) & '0';

when "100" =>-- U2/

y <= '0' & a(width-1 downto 1);

when "101" =>-- 2/

y <= a(width-1) & a(width-1 downto 1);

when "110" =>-- TRUE

y <= true;

when others =>-- FALSE

y <= false;

end case;

end process alu_1;

end alu1_arch;


Logic design fundamentals 2

ALU2

Arithmetic and Logic Instructions


Logic design fundamentals 2

alu2.vhd

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_unsigned.all;

entity alu2 is

generic(width:positive);

port (

a: in STD_LOGIC_VECTOR(width-1 downto 0);

b: in STD_LOGIC_VECTOR(width-1 downto 0);

sel: in STD_LOGIC_VECTOR(2 downto 0);

y: out STD_LOGIC_VECTOR(width-1 downto 0)

);

end alu2;


Logic design fundamentals 2

architecture alu2_arch of alu2 is

begin

alu_2: process(a, b, sel)

variable true, false: STD_LOGIC_VECTOR (width-1 downto 0);

variable Z: STD_LOGIC;

begin

Z := '0';

for i in 0 to width-1 loop

true(i) := '1'; -- true is all ones;

false(i) := '0'; -- false is all zeros

Z := Z or a(i); -- Z = '0' if all a(i) = '0'

end loop;

case sel is

when "000" =>-- +

y <= a + b;

when "001" =>-- -

y <= b - a;

when "010" =>-- AND

y <= a and b;

when "011" =>-- OR

y <= a or b;

when "100" =>-- XOR

y <= A xor B;


Logic design fundamentals 2

when "101" =>-- 0= NOT

if (Z = '0') then

y <= true;

else

y <= false;

end if;

when "110" =>-- 0<

if (a(width-1) = '1') then

y <= true;

else

y <= false;

end if;

when "111" =>-- U>

if (b > a) then

y <= true;

else

y <= false;

end if;

when others =>

null;

end case;

end process alu_2;

end alu2_arch;


Logic design fundamentals 2

ALU3

Comparators


Logic design fundamentals 2

alu3.vhd

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_arith.all;

use IEEE.std_logic_unsigned.all;

entity alu3 is

generic(width:positive);

port (

a: in STD_LOGIC_VECTOR(width-1 downto 0);

b: in STD_LOGIC_VECTOR(width-1 downto 0);

sel: in STD_LOGIC_VECTOR(2 downto 0);

y: out STD_LOGIC_VECTOR(width-1 downto 0)

);

end alu3;


Logic design fundamentals 2

architecture alu3_arch of alu3 is

begin

alu_3: process(a, b, sel)

variable true, false: STD_LOGIC_VECTOR (width-1 downto 0);

variable avs, bvs: signed(width-1 downto 0);

begin

for i in 0 to width-1 loop

true(i) := '1'; -- true is all ones;

false(i) := '0'; -- false is all zeros

avs(i) := a(i);

bvs(i) := b(i);

end loop;

case sel is

when "000" =>-- =

if (a = b) then

y <= true;

else

y <= false;

end if;


Logic design fundamentals 2

when "001" =>-- <>

if (a /= b) then

y <= true;

else

y <= false;

end if;

when "010" =>-- U<

if (b < a) then

y <= true;

else

y <= false;

end if;

when "011" =>-- U>

if (b > a) then

y <= true;

else

y <= false;

end if;

when "100" =>-- U<=

if (b <= a) then

y <= true;

else

y <= false;

end if;


Logic design fundamentals 2

when "101" =>-- <

if (bvs < avs) then

y <= true;

else

y <= false;

end if;

when "110" =>-- >

if (bvs > avs) then

y <= true;

else

y <= false;

end if;

when "111" =>-- <=

if (bvs <= avs) then

y <= true;

else

y <= false;

end if;

when others =>

null;

end case;

end process alu_3;

end alu3_arch;


Logic design fundamentals 2

0

1

2

3

4

5

6

7

85

C4

E6

addr(2:0)

M(7:0)

55

67

D4

F4

C6

ROM


Logic design fundamentals 2

0

1

2

3

4

5

6

7

85

C4

E6

addr(2:0)

M(7:0)

55

67

D4

F4

C6

ROM.vhd

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_unsigned.all;

entity ROM is

port (

addr: in STD_LOGIC_VECTOR (2 downto 0);

M: out STD_LOGIC_VECTOR (7 downto 0)

);

end ROM;


Logic design fundamentals 2

0

1

2

3

4

5

6

7

85

C4

E6

addr(2:0)

M(7:0)

55

67

D4

F4

C6

architecture ROM_arch of ROM is

constant data0: STD_LOGIC_VECTOR (7 downto 0) := "10000101";

constant data1: STD_LOGIC_VECTOR (7 downto 0) := "11000100";

constant data2: STD_LOGIC_VECTOR (7 downto 0) := X"E6";

constant data3: STD_LOGIC_VECTOR (7 downto 0) := X"55";

constant data4: STD_LOGIC_VECTOR (7 downto 0) := X"67";

constant data5: STD_LOGIC_VECTOR (7 downto 0) := X"D4";

constant data6: STD_LOGIC_VECTOR (7 downto 0) := "11110100";

constant data7: STD_LOGIC_VECTOR (7 downto 0) := "11000110";

type rom_array isarray (NATURAL range <>) of STD_LOGIC_VECTOR (7 downto 0);

constant rom: rom_array := (

data0, data1, data2, data3,

data4, data5, data6, data7

);

begin

process(addr)

variable j: integer;

begin

j := conv_integer(addr);

M <= rom(j);

end process;

end ROM_arch;


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