CMPT 250 Computer Architecture

1. CMPT 250 Computer Architecture Instructor: Yuzhuang Hu yhu1@cs.sfu.ca

2. The Shifter • 3 clock cycles will be needed if using a bidirectional shift register with parallel load. • A clock pulse loads the output of Bus B into the shift register. • Another clock pulse performs the shift. • Another clock pulse transfer the result to the destination register.

3. B B B B 3 2 1 0 Serial output L Serial output R I I R L M M M M 0 1 2 0 1 2 0 1 2 0 1 2 S S S S U U U U X X X X 2 S H H H H 3 2 1 0 A Faster Approach: Combinational Shifters • Input IR: right shift, IL: left shift. Output R: right shift, L: left shift.

4. D D D D 3 2 1 0 S 0 S 1 3 2 1 0 S S 3 2 1 0 S S 3 2 1 0 S S 3 2 1 0 S S 1 0 1 0 1 0 1 0 M M M M U U U U X X X X Y Y Y Y 3 2 1 0 4-Bit Barrel Shifter • Depending on S, the barrel shifter can shift or rotate the input data by several bits.

5. Function Table for 4-Bit Barrel Shifter

6. Datapath Representation n • Reduce the apparent complexity of the datapath with a hierarchical structure. • The registers, and the multiplexer, decoder, and enable hardware for accessing them are encapsulated into a register file. • The ALU, shifter, Mux F and status bits are encapsulated into a function unit. • The details of the register file and the function unit are now at a lower design hierarchy. D data Write m D address m 2 n x Register file m m A address B address A data B data Constant in n n n 1 0 MB select MUX B n Bus A Address out Bus B n Data out A B 4 FS V Function C unit N Z F n n Data in 0 1 MD select MUX D

8. Register File • A set of registers having common micro-operations performed on them may be organized into a register file. • The typical register file is a special type of fast memory that permits one or more words to be read or written, all simultaneously.

9. MF G H FS(3:0) Select Select(3:0) Select(3:0) Micr ooperation ¬ 0000 0 0000 XX F A ¬ + 0001 0 0001 XX F A 1 + ¬ 0010 0 0010 XX F A B ¬ + + 0011 0 0011 XX F A B 1 + ¬ 0100 0 0100 XX F A B + ¬ + 0101 0 0101 XX F A B 1 ¬ - 0110 0 0110 XX F A 1 ¬ 0111 0 0111 XX F A ¬ Ù 1000 0 1 X 00 XX F A B ¬ Ú 1001 0 1 X 01 XX F A B ¬ Å 1010 0 1 X 10 XX F A B ¬ 1011 0 1 X 11 XX F A ¬ F B 1100 1 XXXX 00 ¬ F sr B 1101 1 XXXX 01 ¬ 1110 1 XXXX 10 F sl B G Select, H Select, and MF Select Codes Defined in Terms of FS

10. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 M M R D A AA BA FS B D W Control word The Control Word • There are 16 binary control inputs to the datapath. Their combined values specify a control word. • Recall that • DA: destination register address. • AA and BA: the addresses of A and B operands. • MB and MD: selects muxes B and D respectively. • FS : function select for the function unit. • RW : write to the register file.

11. n D data R W 0 Write 15 D A 14 D address 13 8 n x Register file 12 9 A address B address AA BA 11 8 7 10 A data B data n n n Constant in 1 0 6 MB MUX B Bus A n Address out Bus B n Data out A B V 5 Function C 4 FS unit N 3 Z 2 n n Data in 0 1 MD 1 MUX D Bus D Block Diagram

12. Examples of Microoperations for the Datapath: Symbolic Representation Micr o- op eratio n D A A A B A M B F S M D R W ¬ R 1 R 2 R 3 R 1 R 2 R 3 R e g ister F A B 1 F unction Write – = + + ¬ R 4 s l R6 R 4 — R 6 R e g ister F sl B F unction Write = ¬ R 7 R 7 1 R 7 R 7 — Re gister Function Write F A 1 + = + ¬ R 1 R 0 2 R 1 R 0 — Con s tant Func tio n Write + F A B = + ¬ Data out R 3 —— R 3 R eg i s t e r — — N o Wr it e ¬ R 4 D ata in R 4 —— — — Data in Write ¬ Å R 5 0 R 5 R 0 R 0 R e g ister F A B F unction Write =

13. Micr o- o p eratio n D A A A B A M B F S M D R W ¬ 1 2 3 0 0 1 0 1 0 011 0 010 1 0 1 R R R – ¬ 4 s l R6 10 0 110 0 111 0 0 1 R XX X ¬ 7 7 1 11 1 1 11 0 000 1 0 1 R R XXX + ¬ 1 0 2 00 1 0 00 1 001 0 0 1 R R XXX + ¬ Data out 3 011 0 0 R XX X X XX XXX X X ¬ 4 D ata in 10 0 1 1 R XX X XXX X XXX X ¬ 5 0 1 0 1 0 0 0 000 0 101 0 0 1 R Examples of Microoperations for the Datapath: Binary Representation

14. Simulation of the Microoperation Sequence

15. A Simple Computer Architecture • Instruction Set Architecture: defines the boundary between hardware and software. • An instruction is a collection of bits that instructs the computer to perform a specific operation. • We call the collection of instructions for a computer its instruction set and a thorough description of the instruction set its instruction set architecture(ISA).

16. Storage Resources • The following diagram depicts the computer structure as viewed by a user programming it in a language that directly specifies the instructions to be executed. Program counter (PC) Instruction memory 15 x 2 16 Register file x 8 16 Data memory x 15 2 16

17. 15 9 8 6 5 3 2 0 Destination Source reg- Source reg- Opcode register (DR) ister A (SA) ister B (SB) (a) Register 15 9 8 6 5 3 2 0 Destination Source reg- Opcode Operand (OP) register (DR) ister A (SA) (b) Immediate 15 9 8 6 5 3 2 0 Address (AD) Address (AD) Source reg- Opcode (Left) (Right) ister A (SA) (c) Jump and Branch Three Instruction Formats • An instruction consists of an operation code, several fields about the operands, and possibly a field about the location to store the result.

18. 15 9 8 6 5 3 2 0 Destination Source reg- Source reg- Opcode register (DR) ister A (SA) ister B (SB) (a) Register Register Instructions • SA: Source Register A, SB: Source Register B, DR: Destination Register. • Consider the instruction R1 <- R2 + R3. Here SA=R2, SB=R3, DR=R1.

19. 15 9 8 6 5 3 2 0 Destination Source reg- Opcode Operand (OP) register (DR) ister A (SA) (b) Immediate Immediate Instructions • SA: source register A, DR: Destination register OP: an immediate number. • Consider the instruction R0 <- R1 + 3. Here SA = R1, OP = 3, DR = R1.

20. 15 9 8 6 5 3 2 0 Address (AD) Address (AD) Source reg- Opcode (Left) (Right) ister A (SA) (c) Jump and Branch Jump and Branch Instructions • SA : source register A. • AD left + AD right : a number with signed 2s complement representation. • Consider the instruction 1100000 101 110 100. Here SA=R6, AD=-20. It is equivalent to “If R6=0, PC<-PC-20.”

21. Instruction Specifications for the Simple Computer

22. Memory Repr esentation of Instruc t ions and Data D eciimal Dec i mal Ad d r ess Mem o r y C ontents Op cod e Other F i elds Op eration ¬ - 25 00001 01 001 010 011 5 (Subtract) DR:1, SA:2, SB:3 R1 R2 R3 ¬ 35 01000 00 000 100 101 32 (Store ) S A:4, SB:5 M[ R4] R5 ¬ + 3 45 10000 10 010 111 011 66 (Add DR: 2 , S A : 7 , OP :3 R 2 R7 Im mediate) 55 11000 00 101 110 100 96 (Branch AD: 44, SA:6 If R6 = 0, ¬ - on Z e ro ) PC PC 20 70 000 000000110 00000 Data = 1 92. Aft e r execution of instruction in 35, Data = 8 0 . Memory Representation of Instructions and Data

23. Block Diagram for a Single-Cycle Computer

24. Control Unit of the Single Cycle Simple Computer • We have described the design of its datapath. • The block diagram for this computer has a hardwired control unit that fetches and executes an instruction in a single clock cycle. • We do not write to the instruction memory, making it appear in this model to be a combinational rather than a sequential component.

25. The Program Counter (PC) • The PC provides the instruction address to the instruction memory. • The PC is updated in each clock cycle. The behaviour of the PC is determined by the opcode, N, and Z.

26. THANKS!