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MOSFET CHARACTERIZATION LAB. How to Find K and Vto o. How to Find K and Vto o. ohmic contact effect. slope = . to be discussed in a future slide. V GS. Vto o. How to Find K and Vto o. Sub-threshold Conduction. ln(I D ). leakage. Vto. V GS. Sub-threshold Conduction.

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How to find k and vto o1
How to Find K and Vtoo

ohmic contact effect

slope =

to be discussed in

a future slide

VGS

Vtoo



Sub threshold conduction
Sub-threshold Conduction

ln(ID)

leakage

Vto

VGS





Finding l
Finding l

triode: VDS < VGS - Vtoo

saturation:

VDS > VGS - Vtoo

ID

VGS3 > VGS2

VGS2 > VGS1

VGS1 > Vtoo

VDS

-1 / l



Instructions for mosfet characterization lab 1
Instructions for MOSFET Characterization Lab (1)

a) Find k and Vto for the NMOS device of the CD 4007.

Use the circuit below:

Important: Current (I) should not exceed 5 ma !

Also connected to pin 14 putting all PMOS bodies at VDD

U13

PIN5

+

VGS = VDS

PIN3

-

Also connected to pin 7 putting all NMOS bodies at Vss

U15

PIN4

I

U17

U18

Note: with VGS = VDS, we require VGS – Vto < VDS so the device is in saturation.

Take enough points to get a reasonable curve to find k and Vto, as well as observing the

sub-threshold and ohmic regions.


Instructions for mosfet characterization lab 2
Instructions for MOSFET Characterization Lab (2)

b) For the NMOS device of the CD4007, find the full-drain characteristics for

VGS = 2, 3, 4, 5 Volts. Use the data to find l.

U5

U3

U9 must be connected to U8

I

Pin 5

U11

+

U12

VDS

Pin 3

-

+

Pin 4

Also connects to pin 7 putting all NMOS bodies at Vss

VGS

-

U9

U10

U7

Important: Limit VDS to 10 Volts and I to 5 ma. The device goes into the

non-saturation region when VGS – Vto > VDS. Do not use this data to calculate l.


Instructions for mosfet characterization lab 3
Instructions for MOSFET Characterization Lab (3)

c) Repeat part (a) for the PMOS device of a CD 4007 and find k and Vtoof the device.

Note Vto is negative.

A PMOS device is in saturation when VDS < VGS – Vto where VGS and VDS are negative for a PMOS enhancement device. With VGS = VDS, VDS is always less than VGS – Vto . Conclusion: for the circuit below, the device is always saturated.

U15 must be connected to U18

Pin 14 also puts all PMOS bodies at VDD

U13

PIN14

+

PIN6

Vpower supply

=(-VGS) = (-VDS)

-

PIN13

U14

U17

I

U16

Also connected to pin 7 Puts all NMOS bodies at ground

Take enough points to get a reasonable curve to find k and Vto, as well as observing the sub-threshold and ohmic regions.


Instructions for mosfet characterization lab 4
Instructions for MOSFET Characterization Lab (4)

d) Repeat part (b) for the PMOS device of a CD 4007. Use VGS = -2, -3, -4, and –5 Volts.

Find l. l should be negative since ID = K (VGS – Vto)2(1 + lVDS) and VDS is negative.

U7

+

U9

U10

V power supply 2 = (-VGS)

PIN14

Vpower supply 1 = (-VDS)

+

U1

-

-

PIN6

U4

PIN13

U5

I

U3

Pin 14 also puts all PMOS bodies at VDD

U2 must be connected to U9

Important: Limit VDS to –10 volts and I to 5 ma. The device goes into its

non-saturation region when VGS – Vto < VDS. Do not use this data to calculate l.


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