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Statistical Full-Chip Leakage Analysis Considering Junction Tunneling Leakage. Tao Li Zhiping Yu Institute of Microelectronics Tsinghua University. Outline. Motivation Junction Tunneling Leakage – Circuit Level Analysis Simple inverter Multi-input gate

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statistical full chip leakage analysis considering junction tunneling leakage

Statistical Full-Chip Leakage Analysis Considering Junction Tunneling Leakage

Tao Li Zhiping Yu

Institute of MicroelectronicsTsinghua University

outline
Outline
  • Motivation
  • Junction Tunneling Leakage – Circuit Level Analysis
    • Simple inverter
    • Multi-input gate
  • Statistical Full-Chip Leakage Analysis Technique
    • Modeling of process-induced parameter variations
      • PCA & ICA
    • Sum of leakage components
  • Experimental Results
  • Summary
leakage and process variations

0.18 μm

0.09 μm

65 nm

250

Leakage Power

Active Power

200

150

Power (W)

100

50

0

0.1

0.25

0.18

0.13

Leakage and Process Variations
  • Leakage power becomes a major component ofthe total power.
  • Process variation has a significant impact on leakage.

Feature Size

Scale Down

major leakage components
Major Leakage components
  • Subthreshold leakage
  • Gate oxide leakage
  • Junction tunneling leakage

Gate Leakage Igate

Subthreshold Leakage Isub

Gate

Source

Drain

n+

n+

Bulk

Junction tunneling leakage

overview of related works
Overview of Related Works
  • Previous works on statistical full-chip leakage computation
    • Computation of PDF of full-chip leakage
      • Approximate process variations asGaussian distributions
      • Finding full-chip leakage by summing upindependent lognormals
      • R. Rao ISLPED03,H. Chang ICCAD 03,H. Chang DAC05, X. Li DAC06, et al.
  • Most of the previous works ignored
    • Effect of Non-Gaussian parameters
    • Junction tunneling leakage
outline6
Outline
  • Motivation
  • Junction tunneling leakage – Circuit level analysis
    • Simple inverter
    • Multi input gate
  • Statistical Full-chip leakage analysis technique
    • Modeling of process-induced parameter variations
      • PCA & ICA
    • Sum of leakage components
  • Experimental Results
  • Summary
simple inverter

0

Simple Inverter
  • When input = 0V
    • NMOS: maximum &
      • Can be independently calculated and added for total leakage
    • PMOS: gate oxide leakage – small and ignored
  • When input =
    • NMOS: gate oxide leakage
    • PMOS: subthreshold leakage and junction tunneling leakage

0

multi input gate general approach
Multi input gate: general approach
  • If all inputs have a high state
    • Analysis is similar to the that of the inverter
  • At least one input is low
    • Combination of , ,and
    • Approach: distinguish 6 different scenarios
computation of total chip leakage
Computation of Total Chip Leakage
  • Total leakage current of a chip:

: probability of input vector state i of the jth gate

can be either the leakage for a fixed input vector or the average leakage current

  • Input pattern independent approach
    • Direct computation: 2k input vector states for a k-input gate
    • Applying dominant states of
  • Leakage of stack at state i is not always independent
    • Interactions ofIsub,Igateand Ijunc need to be considered
    • Analyzing leakage current of stack by input state
dominant states of leakage current
Dominant States of Leakage Current
  • Interaction between Isub and Igate
  • Case (a) (c): dominate states of Igate

NMOS-Transistor Stack

D. Lee et. al. at DAC03

C. Oh et. al. at DAC99

D. Lee et. al. at DAC03

  • Case (a) (b): dominate states of Isub
  • Dominant states of junction tunneling leakage Ijunc
    • States with the “on” transistors connected to the output node(stack effect )
    • Only k dominant states for a k-input gate
results leakage estimation for 4 nand
Results: Leakage estimation for 4-NAND
  • The error of the proposed analysis method over SPICE
  • Average ~1.5% over all input states
  • Maximum error = 4.5% @1110
outline12
Outline
  • Motivation
  • Junction tunneling leakage – Circuit level analysis
    • Simple inverter
    • Multi input gate
  • Statistical Full-chip leakage analysis technique
    • Modeling of process-induced parameter variations
      • PCA & ICA
    • Sum of leakage components
  • Experimental Results
  • Summary
proposed analysis method highlights
Proposed Analysis Method Highlights

Non-Gaussian and Gaussian variables transformed

to independent basis with PCA/ICA

Incorporates both Gaussian

and non-Gaussian parameters

Inputs are moments of varying process parameters

Easier to obtain moments from process data files

Three kinds of leakage components are considered

Fast algorithm for the sum up of leakage components

Moments matching-based

PDF/CDF extraction

Uses closed form PDF/CDF

expressions

outline14
Outline
  • Motivation
  • Junction tunneling leakage – Circuit level analysis
    • Simple inverter
    • Multi input gate
  • Statistical Full-chip leakage analysis technique
    • Modeling of process-induced parameter variations
      • PCA & ICA
    • Sum of leakage components
  • Experimental Results
  • Summary
experimental results
Experimental Results
  • Comparison of our results with Monte Carlo simulations
  • Comparison with Gaussian modeling of parameters
outline16
Outline
  • Motivation
  • Junction tunneling leakage – Circuit level analysis
    • Simple inverter
    • Multi input gate
  • Statistical Full-chip leakage analysis technique
    • Modeling of process-induced parameter variations
      • PCA & ICA
    • Sum of leakage components
  • Experimental Results
  • Summary
summary
Summary
  • A fast approach to compute total leakage current
    • Considering , ,and
    • Average error 1.5%
  • Both Gaussian and Non-Gaussian parameters are considered
    • PCA and ICA are employed as preprocessing steps
  • Sum the leakage to get a final result
  • Algorithm has a complexity of
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