Interconnect Working Group

1. Interconnect Working Group ITRS 2004 Update 14 July 2004 San Francisco

2. ITWG Regional Chairs Japan Tujimura -san Hideki Shibata Taiwan Douglas CH Yu US Robert Geffken Christopher Case Europe Hans Joachim-Barth Korea Hyeon-Deok Lee Hyun Chul Sohn

3. Agenda • Interconnect scope • Highlight of changes • Difficult challenges • Review of key issues on materials • Reliability • Technology requirements issues • Table updates • Interconnect performance • Last words

4. Interconnect scope • Conductors and dielectrics • Metal 1 through global levels • Starts at pre-metal dielectric (PMD) • Associated planarization • Necessary etch and surface preparation • Embedded passives • Reliability and system and performance issues • Ends at the top wiring bond pads • Predominantly “needs” based, with some important exceptions (k and resistivity)

5. Typical MPU cross section

6. 2004 highlights • Minor changes to low k roadmap • Color changes only bulk and effective targets remain the same • Metal one MPU driver matched to overall nodes • Clarification of metal one versus local wiring • Updated wiring performance metrics • New metrics associated with the increase in Cu resistivity due to scattering • Updated Jmax specification • Updated contact resistance • Updated surface preparation metrics

7. Introduction of new materials to meet conductivity requirements and reduce the dielectric permittivity* Engineering manufacturable interconnect structures compatible with new materials and processes* Achieving necessary reliability Three-dimensional control (3D CD) of interconnect features (with its associated metrology) is required to achieve necessary circuit performance and reliability. Manufacturability and defect management that meet overall cost/performance requirements Mitigate impact of size effects in interconnect structures Three-dimensional control (3D CD) of interconnect features (with its associated metrology) is required. Patterning, cleaning, and filling at nano dimensions Integration of new processes and structures, including interconnects for emerging devices Identify solutions which address global wiring scaling issues* Difficult Challenges >45 nm <45 nm * Top three grand challenges

8. Engineering manufacturable structures • Combinations and interactions of new materials and technologies • interfaces, contamination, adhesion, diffusion, leakage concerns, CMP damage, resist poisoning, thermal budget, ESH, CoO • Structural complexity • levels - interconnect, ground planes, decoupling caps • passive elements • mechanical integrity • other SOC interconnect design needs (RF) • cycle time

9. Materials Challenges • Long term – size effects • Microstructural and atom scale effects • Continued introduction of materials • barriers/nucleation layers for alternate conductors - optical, low temp, RF, air gap • alternate conductors, cooled conductors • More reliability challenges

10. Reliability Challenges • Short term • New failure mechanisms with Cu/low k present significant challenges before volume production • Electrical, thermal and mechanical exposure • interface diffusion • interface delamination • Higher intrinsic and interface leakage in low k • Need for new failure detection methodology to establish predictive models

11. Attaining Dimensional Control • 3D CD of features • Multiple levels • performance and reliability implications • reduced feature size, new materials and pattern dependent processes • Process problems • Line edge roughness, trench depth and profile, via shape, etch bias, thinning due to cleaning, CMP effects. • Process interactions • CMP and deposition - dishing/erosion - thinning • Deposition and etch - to pattern multi-layer dielectrics • Patterning, cleaning and filling at nano dimensions • particularly DRAM contacts and dual damascene

12. Technology Requirements • Wiring levels including “optional levels” • Reliability metrics • Minimum wiring/via pitches by level • Performance metric • Planarization requirements • Conductor resistivity • Barrier thickness • Dielectric metrics including effective k

13. MPU HP Near Term Years New RC delay metric for a 1 mm line (level dependent) – adjusted for anticipated impact of Cu resistivity rise

14. MPU HP Near Term Years Cu at all nodes - conformal barriers – resistivity 2.2 mW-cm

15. Model for Calculating Copper Wire Resistivity Increase due to Electron-scattering Effect ρ(W)=ρ0[1+(λ/W)[3/4(1-p)+3/2(r/1-r)]] ρo=ρ(phonon scattering)+ρ(impurities, vacancies, dislocations) = constant(1.9μΩcm@300K) λ=MFP(mean free path of charge carriers)=3.4×10-6cm W=wire width(cm) ｒ= probability for reflection of electrons at the grain boundaries=0.2 p= portion of electron specularly reflected from the wall=0.5

16. p=0(complete diffuse scattering) 5 p=0.3 Measured Cu resistivity without BM Updated(May2004) 4 ρ(Al):2.74μΩcm 3 Resistivity(μΩcm) 2 p=0.5 1 0 0 100 200 300 400 500 Wire width(nm) Cu Wire Resistivity Increase by Electron-scattering Effect From Leti Arnaud-san New experimental results calculated with ρo = 1.8 μΩcm, λ = 40 nm, p= 0.6, r= 0.2 Experimental results shown at IITC 2003 p. 133

17. ρ and ρeff Calculation Result for Each Wire Level Metal1 Wiring Intermediate Wiring Global Wiring

18. ρ and ρeff Calculation Result for M1 Wire Level for Every Year

19. Cu resistivity increase 5 p=0 Measured Cu resistivity without barrier material 4 3 Resistivity(μΩcm) 2 p=0.5 1 0 0 0.1 0.2 0.3 0.4 0.5 Line width (nm) Wire width < mean free path of electrons ↓ Surface scattering dominant p=0 (complete diffuse scattering) p=1 (specular scattering) ↓ Resistivity increases even if the barrier metal Is 0 thickness ↓ barrier/Cu interface smoothing might be a solution p: fraction of electrons having elastic collisions at wire surfaces

20. k effective roadmap discussion Currently introduced in volume production – behind schedule • Significant innovation required in the areas of • Damage-free etch, ash and • clean • Damage-free integration • Low k materials Keff = 3.1 could be achieved by integration of dense 2.7- type material with SiC-based assist layer at k=4.5 • Keff = 2.7 cannot be achieved by • integration of a dense 2.7- • type material with SiC-based • assist layers at k=4.5 • or a porous 2.4 material if • sidewall etch damage occurs • even without etch-stop • Introduction of lower k hardmask and etch-stop layers required to achieve keff • Keff = 2.5 will require: • Bulk low k of <2.2 with • minimal sidewall damage • low k hardmask and etch- • stop layers (k<2.8) • Elimination of trench etch- • stop desirable • Introduction of metal cap and low k diffusion barrier/vias etch-stop

21. MPU HP Long Term Years Conductor effective resistivity (red) because of scattering effects - research required Atomic dimension barriers – zero thickness barrier desirable but not required

22. Updated Jmax Table (Near-term)

24. Modulus vs k-value Low-k materials from Applied Materials, ASM, Dow Chemical, Honeywell, JSR, Novellus

25. Technology Requirements Near Term: Modifications of Low-k Material and CD Metrics Dielectric Constant Delta: Take into Account Total Clean Process Add Profile Change as Metric

26. Technology Requirements Near Term: Post-CMP Cleaning Metrics New Format Proposed with Focus on Post-CMP Clean Watermarks and Surface Roughness of Cu Included

27. Surface preparation • Cross TWG work from FEP • Technology requirements address: • Killer defect density and size • Back surface particles • Metallic and organic contamination • Dielectric constant change (increase) due to stripping, cleaning and rework

28. Cross TWG Issues • Metrology • Discussion on need for in-line texture measurements – no • Need owner for precision gas and liquid flow specifications for new processes such as ALD • Possible need for in-line etch depth monitoring for etch-stop free dual damascene • Factory Integration • Discussed trends in some 300 mm processes which show dramatic rise in gas consumption that are not scaling from 200 mm • Yield - Long list of addressable issues related to contamination and purity of fluids and precursors, slurry characterization • ESH • Clarification of dilute Cu waste stream reclaim/recovery • Plan to introduce new metrics related to precursor (or other material) utilization efficiency • Need to identify chamber cleaning gases (which are increasing rapidly for 300 mm single wafer) for reduction • Begin 2005 task to renew table of hazardous materials • A&P • Interconnect will provide mechanical properties of dielectric stack • Test – concerns over mechanical damage to weaker dielectrics from probing

29. 2005 Thoughts • Metal 1 design rule concerns • Resolved confusion over non -contacted versus contacted half-pitch and the incorrect use of technology node for MPU • Recent publications suggest M1 scaling may be accelerating • Desirable to have separate tables for high performance • High performance MPU pitches scaling at ~0.7/3 years • High performance ASIC pitches scaling at ~0.75-0.8/ 2 years • Decoupled from DRAM at 0.7/3 years • Dialog started with Design, A&P and Test to identify directions for 3D ICs – may address global wiring problem

30. Global interconnect roadmap

31. Last words • Continued changes in materials • Develop solutions for emerging devices • Must manage 3D CD • System level solutions must be accelerated to address the global wiring grand challenge • Cu resistivity increase impact appears ~2006 • materials solutions alone cannot deliver performance - end of traditional scaling • integrated approach with design and packaging