Procstar iii performance charactarization
Download
1 / 22

PROCStar III Performance Charactarization - PowerPoint PPT Presentation


  • 104 Views
  • Uploaded on

Midterm Presentation. PROCStar III Performance Charactarization. Instructor : Ina Rivkin Performed by : Idan Steinberg Evgeni Riaboy Semestrial Project Winter 2010. Agenda. Project Overview Project Goals Progress Tests Overview Example exercise Timeline.

loader
I am the owner, or an agent authorized to act on behalf of the owner, of the copyrighted work described.
capcha
Download Presentation

PowerPoint Slideshow about ' PROCStar III Performance Charactarization' - long


An Image/Link below is provided (as is) to download presentation

Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author.While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server.


- - - - - - - - - - - - - - - - - - - - - - - - - - E N D - - - - - - - - - - - - - - - - - - - - - - - - - -
Presentation Transcript
Procstar iii performance charactarization

Midterm Presentation

PROCStar III Performance Charactarization

Instructor:Ina RivkinPerformed by:Idan Steinberg EvgeniRiaboy

Semestrial Project

Winter 2010


Agenda
Agenda

  • Project Overview

  • Project Goals

  • Progress

  • Tests Overview

  • Example exercise

  • Timeline


Project overview
Project Overview

  • With the introduction of a new FPGA based board, we have to devise a series of tests to examine the devices max practical performance, allowing the students that use these boards for future projects, to plan optimal design based on the concluded tested performance.

  • All the tests are intended to determine maximal frequency that ensure correct results (this is why we check all the data for correctness).


Gidel procstar iii stratix iii 260e
GidelPROCstar III Stratix III 260E

  • 4 AlteraStratix III 260E FPGA’s, with 256 MB on chip memory

  • 8 Lane PCIe host interface

  • 8 DDR2 Banks, with 2*2GB on first FPGA, and 1*2GB on the other FPGA’s

  • ~2MB FPGA Internal RAM

  • 255K Logic Elements (per FPGA)


The procstar iii processing unit
ThePROCStar III Processing Unit


Project goals
Project Goals

Testing Procstar III board for:

  • Maximum frequency of reading/writing between the FPGA and Memory Banks

  • Maximum communication speed between FPGA’s, both on their adjacent connection and on their shared BUS.

  • Highest possible performance of the internal logic in Add, Subtract, Multiply, Divide and sqrt configurations.


Progress
Progress

  • Learning different tools for the FPGA environment

  • Preparing several exercises

    • implementing work with different memory configurations – in both FIFO and Multiport

    • work between two separate FIFO’s on different DDR’s

    • Counter unit (for performance measurement)

  • Preparing a C code that interacts with the Proc board, to serve as a user interface

  • Preparing a general example

  • Preparing the required tests

  • Concluding performance results


Project plan
Project Plan

Test 1: External Memories Transfer Rate:

  • We will fill the memory with data (from the PCI) , and test it by reading/writing the data between the memory and the FPGA, thus determining the transfer rate (between the FPGA and the Memory bank), both in Multi FIFO and Multi Port Configurations. We will Perform the test at different frequencies to determine the maximal

    frequency of data

    transfer between

    Memory bank and FPGA.

Procstar III

FPGA

Memory Bank


Project plan1
Project Plan

Test 1:

  • Firstly, the data will be transferred from the PC to the Memory bank by a C code program

  • The test will be performed at increasing frequencies, to determine maximal frequency

  • Then, the data will be read by the FPGA from the memory bank and checked for correctness

  • The measuring will be done by a counter unit on the FPGA, which sums the clock cycles during the test, which will start at the same time with the FPGA reading


Project plan2
Project Plan

Tests 2,3: FPGA Communication:

We will test the communication between the FPGA’s, both on their adjacent connection and their shared BUS.


Project plan3
Project Plan

Test 2: FPGA Communication:

We will build a state machine that creates 3-4 different outputs on one FPGA, transfer the data to an adjacent FPGA on their direct connection, and check the data correctness (running at increasing frequencies on the data channel).

Procstar III

FPGA 1

FPGA 2


Project plan4
Project Plan

Test 2: FPGA Communication:

  • To establish connection between two FPGA’s, we will use a basic protocol on the communication channel of the adjacent FPGA’s.

  • It will be based on a simple control channel that indicates valid data on the shared channel between the FPGA’s.

  • The test will be complied from creating several outputs on one FPGA, transferring it to the Adjacent FPGA and checking it(running at increasing frequencies on the data channel).

  • The measuring will be done by a counter unit on the second FPGA, which will count the cycles from the beginning of data transfer till the end of it.


Project plan5
Project Plan

Test 3: FPGA Communication:

We will build a state machine that creates 3-4 different outputs on one FPGA, transfer the data to the other FPGA’s on their BUS connection, and check the data correctness.

Procstar III

BUS

FPGA 1

FPGA 2

FPGA 3

FPGA 4


Project plan6
Project Plan

Test 3: FPGA Communication:

  • This test will be executed the same way as test 2, only using different data and control channels (connecting all 4 FPGA units).


Project plan7
Project Plan

Test 4: Internal Functions Testing:

We will perform different mathematical operations:

  • Add

  • Subtract

  • Multiply – both in LE and in DSP blocks

  • Divide

  • Sqrt

    For fixed point and floating point operations, determining the DSP and LE performance.


Project plan8
Project Plan

Test 4: Internal Functions Testing:

  • The testing will be performed by creating data from a state machine on the FPGA and performing the tested operation.

  • The Add, Subtract, Divide and sqrt will be performed in VHDL code.

  • The Multiply operation will be performed by the Altera library components in LE and DSP blocks.

  • The counter unit will sum up the clock cycles from the beginning of the operation till its end.

  • The tests will be performed at different frequencies, determining the maximal working frequency.


Project plan9
Project Plan

Test 5: PC to Memories Transfer Rate:

  • We will fill a memory bank with data from the PCI, and read it back, thus determining the transfer rate from the PC to the Memory bank on Proc Board. Then we will be able to compare the result with test 1, where we have tested the FPGA to memory transfer rate.

Procstar III

Stratix III

Memory Bank

PCIe Controller (DMA Mode)

PCIe


An example exercise was prepared
An example exercise was prepared:

An example with the usage of the required resources for the main project plan – taking data from the PCI, performing mathematical operation and writing it to a DDR:

X2

PCIe

DDRin Multi Port Memory

PCIe



Example exercise1
Example exercise:

We have measured the time it takes from the moment the data is being sent to the Proc board till it has been read on the PC.

Transferring 10 buffers, each buffer of 128 bits, at frequency of main clock = 125 MHz


Example exercise2
Example exercise:

Transferring 1000 buffers, each buffer of 128 bits, at frequency of main clock = 125 MHz



ad