Keh-Jeng Chang, Ph.D. Associate Professor Department of Computer Science National Tsing Hua University, Hsinchu, Taiwan [email protected] Application and Validation of 3D Electromagnetic and Thermal Modeling. Acknowledgements.
The authors want to thank the following institutes for providing this research with generous resources:
Vertical structure of a pixel and its equivalent circuit
Note: Validating mura product defects through 3D TFT-LCD models is an on-going research in NTHU-CS.
Source: Silvaco ‘06
The growing popularity of trough silicon vias (TSV) and on-chip spiral inductaors.
Source: P. Franzon, NCSU, ‘05
Performed in NTHU-CS ‘06
DRC-clean nanometer circuit layouts
Current pseudo 3D layout parameter extraction (LPE)
New 3D layout parameter extraction (LPE)
Timing simulations and clock speed comparisons (We suggest that the new 3D LPE should be adopted if the compared difference is > 10%.)
Complex nanometer 3D profiles for parasitic capacitance models.
Source: UMC ‘03
Source: IWSOC ‘04
Source: IEDM ‘06
Source: ASP-DAC ‘07
Source: IBM/UCLA ISPD’06 paper