Net-Ordering for Optimal Circuit Timing in Nanometer Interconnect Design. M. Sc. work by Moiseev Konstantin Supervisors: Dr. Shmuel Wimer, Dr. Avinoam Kolodny. R i-1. R i. R i+1. V cc. S i. S i+1. V cc. L. W i-1. W i. W i+1. C i-1. C i. C i+1. Problem formulation.
M. Sc. work by Moiseev Konstantin
Supervisors: Dr. Shmuel Wimer, Dr. Avinoam Kolodny
R Interconnect Designi-1
Wires 10 years ago – area capacitance was dominant
Wires today – cross capacitance is dominant
Weak driver Interconnect Design
Circuit timing is better in case B !
Q: Is Elmore delay model good enough for state-of-the-art technology?
A: Fitted Elmore Delay model gives up to 2% error in delay estimation
Total sum of delays:
Worst wire delay:
Worst wire slack:
This property is preserved in all kinds of optimizations discussed
Order of wires is influenced by values of driver resistances only !
Question: Does optimal order exist ???
BMI order provides best sharing of inter-wire spaces
Generate all permutations of wires Interconnect Design
For each permutation solve sizing problem
Find permutation giving minimum delay
Number of optimization variables:
Perform impedance matching by function with parameters (if needed)
Arrange wires in BMI order
Solve sizing problem
Number of optimization variables: orMinimizing total sum of delays - summary
Straight forward solution :
Exhaustive search best delay
Exhaustive search worst delay
20 sets of 5 wires Interconnect Design
Rdr: [0.1 ÷ 2] KΩ
Cl: [10 ÷ 200] fF
Bus width: 12 μm
Technology: 90 nmResults: minmax optimizationbus length influence
Miller coefficients can be presented by the matrix
Minimization problem then is equivalent to :
Peak noise Interconnect Design
Delay uncertaintyDelay uncertainty issue
(A. Vittal et al.,
T. Sato et al.)