Net ordering for optimal circuit timing in nanometer interconnect design
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Net-Ordering for Optimal Circuit Timing in Nanometer Interconnect Design. M. Sc. work by Moiseev Konstantin Supervisors: Dr. Shmuel Wimer, Dr. Avinoam Kolodny. R i-1. R i. R i+1. V cc. S i. S i+1. V cc. L. W i-1. W i. W i+1. C i-1. C i. C i+1. Problem formulation.

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Net-Ordering for Optimal Circuit Timing in Nanometer Interconnect Design

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Net-Ordering for Optimal Circuit Timing in Nanometer Interconnect Design

M. Sc. work by Moiseev Konstantin

Supervisors: Dr. Shmuel Wimer, Dr. Avinoam Kolodny


Ri-1

Ri

Ri+1

Vcc

Si

Si+1

Vcc

L

Wi-1

Wi

Wi+1

Ci-1

Ci

Ci+1

Problem formulation

  • Minimize bus timing by ordering of wires and allocation of wire widths and inter-wire spaces

    • Total width of interconnect structure is given constant A

    • All wires have equal length L

A


Motivation

  • Cross-capacitances between wires in interconnect structures have a major effect on circuit timing

Wires 10 years ago – area capacitance was dominant

Wires today – cross capacitance is dominant


Weak driver

Case A

Case B

Strong driver

Capacitive load

Motivation

  • Relative order of wire drivers in a bus influences circuit timing

Circuit timing is better in case B !


Delay model

  • Elmore approximation for delay together with - model equivalent circuit for wire

  • Miller factor assumed 1 for all wires

  • More general case will be discussed later

Q: Is Elmore delay model good enough for state-of-the-art technology?

A: Fitted Elmore Delay model gives up to 2% error in delay estimation


Objective functions

Total sum of delays:

Worst wire delay:

Worst wire slack:


Agenda

  • Solution for total sum of delays objective function

  • Solution for worst delay objective function

  • Optimization of total sum of delays with cross talk

  • Delay uncertainty issue


Solution for total sum of delays caseconstant wire width

  • Differentiating function with respect to and area constraint and equating derivatives to zero, obtain:

  • Now assume all wires have predefined constant width and get:

This property is preserved in all kinds of optimizations discussed


Solution for total sum of delays caseconstant wire width

  • Substitute obtained relations for spaces to objective function, simplify and obtain:

Order-independent part

Order-dependent part

Order of wires is influenced by values of driver resistances only !

Question: Does optimal order exist ???


BMI order

  • Take wires sorted in descending order of drivers and put alternately to the left and right sides of the bus channel

  • Obtained permutation of wires called Balanced Monotonic Interleaved(BMI) order

BMI order

7

6

5

4

3

2

1

BMI order provides best sharing of inter-wire spaces


Optimal order theorem

  • Define , where - non-decreasing monotonic function and - some permutation of -values

  • Theorem (optimal order):given a bus whose wires are of uniform width , the BMI order of signals in the bus yields minimum total sum of delays.

    • Proof :

      • Order-dependent part of is special case of -sum

      • Prove by induction that -sums are minimized by BMI permutation


Impedance matching

  • Balance the resistance of the driver and resistance of the driven line

  • Mathematically:

  • BMI still holds

  • Simple but practical case:


Solution for general case

  • In general case, wire widths are optimization variables

  • Derivatives with respect to :

  • Theorem (existence): For given set of wires , if for each pair of wires and with drivers and loads and respectively holds and , then optimal order of this set of wires is BMI, under total sum of wire delays objective function.

  • One special case: if all load capacitances are equal, then optimal order is always BMI


Generate all permutations of wires

For each permutation solve sizing problem

Find permutation giving minimum delay

Complexity: exponential

Number of optimization variables:

Perform impedance matching by function with parameters (if needed)

Arrange wires in BMI order

Solve sizing problem

Complexity: linear

Number of optimization variables: or

Minimizing total sum of delays - summary

Straight forward solution :

Our heuristic:


Results: total sum minimizationproblem demonstration on random problem instances

  • 20 sets of 5 wires

  • Rdr: [0.1 ÷ 2] KΩ

    (random)

  • Cl: [10 ÷ 200] fF

    (random)

  • Bus length: 600 μm

  • Bus width: 12 μm

  • Technology: 90 nm


Results: total sum minimizationbus width influence

  • Set of 6 wires

  • Rdr: [0.1 ÷ 2] KΩ

    (random)

  • Cl: 10 fF

  • Bus length: 600 μm

  • Technology: 90 nm


Results: total sum minimizationinterleaved bus

  • Set of 7 wires

  • Rdr: 0.1KΩ and 1.9 KΩ

  • Cl: 50 fF and 5 fF

  • Bus length: 600 μm

  • Bus width: 15 μm

  • Technology: 90 nm


Results: total sum minimizationcomparison of heuristics on random problem instances

Exhaustive search best delay

Exhaustive search worst delay

16.54%

0.63%

100%

0.76%

12.60%

0.63%

16.39%

0.07%

11.28%

9.60%

0.21%

14.10%

0.20%

1st heuristic

0.42%

14.10%

Average:

2nd heuristic


Agenda

  • Solution for total sum of delays objective function

  • Solution for worst delay objective function

  • Optimization of total sum of delays with cross talk

  • Delay uncertainty issue


Solution for minmax case

  • The goal: minimizing maximum wire delay (or slack)

  • Function is not differentiable

  • All wires have the same delay (S. Michaely et al.)

  • Assumptions:

    • wire width is convex monotonic decreasing in driver resistance (impedance matching)

    • Drivers and loads satisfy existence theorem


Solution for minmax case

  • Supposition: In minimization of maximum wire delay, optimal order of wires is BMI

    • Under assumptions of previous slide delay expression can be written as:

  • Edge effects (S. Michaely et. al) can break down optimality of BMI


Results: minmax optimizationbus width influence

  • 20 sets of 5 wires

  • Rdr: [0.1 ÷ 2] KΩ

    (random)

  • Cl: [10 ÷ 200] fF

    (random)

  • Bus length: 600 μm

  • Technology: 90 nm


20 sets of 5 wires

Rdr: [0.1 ÷ 2] KΩ

(random)

Cl: [10 ÷ 200] fF

(random)

Bus width: 12 μm

Technology: 90 nm

Results: minmax optimizationbus length influence


Results: minmax optimizationinterleaved bus

  • Set of 7 wires

  • Rdr: 0.1KΩ and 1.9 KΩ

  • Cl: 50 fF and 5 fF

  • Bus length: 600 μm

  • Bus width: 15 μm

  • Technology: 90 nm


Agenda

  • Solution for total sum of delays objective function

  • Solution for worst delay objective function

  • Optimization of total sum of delays with cross talk

  • Delay uncertainty issue


Crosstalk issue

  • So far: we assumed Miller factor 1

  • In practice: can be 0, 1 or 2

  • Introducing Miller factor changes wire delay equation:

  • The solution will be different according to three cases:

    • Miller factor is equal for all pairs of wires

    • Miller factor different only near walls

    • Each pair of wires has its own different Miller factor


1st case: uniform Miller factor

  • The order-dependent part of objective function is given as:

  • When all Miller coefficients are equal, above expression changes to:

  • Conclusion:

    • Uniform Miller factor doesn’t affect functional form of delay function and therefore optimal order will be BMI

    • Impact of wire ordering emphasized even more


2nd case: almost uniform Miller factor

  • All Miller coefficients in internal inter-wire spaces are equal to

  • Miller coefficients near the walls are

  • Order-dependent part of objective function can be written as:

  • BMI order remains optimal if

  • In other cases order is monotonic but not always BMI

  • Minmax optimization gives the same results


3rd case: non-uniform Miller factor

Miller coefficients can be presented by the matrix

Minimization problem then is equivalent to :

Where and

  • Proved to be NP-complete (A. Vittal et al.)


Agenda

  • Solution for total sum of delays objective function

  • Solution for worst delay objective function

  • Optimization of total sum of delays with cross talk

  • Delay uncertainty issue


Peak noise

Delay uncertainty

Delay uncertainty issue

  • Due to difference in arrival times of signals transmitted by neighbor wires, crosstalk noise is created

  • Crosstalk noise is characterized by two main parameters: peak noise and delay uncertainty

  • Maximum delay uncertainty for a signal in a bus can be expressed as follows:

(A. Vittal et al.,

T. Sato et al.)


Minimization of delay uncertainty

  • Define new objective functions:

    • Total sum of delay uncertainties:

    • Worst delay uncertainty:

    • Experiments show that BMI order leads to minimizing both and


Results: minimization of delay uncertainty

Total sum

  • 20 sets of 5 wires

  • Rdr: [0.1 ÷ 2] KΩ

    (random)

  • Cl: [10 ÷ 200] fF

    (random)

  • Bus length: 600 μm

  • Bus width: 15 μm

  • Technology: 90 nm

Minmax

  • Average improvement:

    • Total sum of delay uncertainties: about 27 %

    • Worst delay uncertainty:

      about 43%


Monotony in ordering optimizations

  • Monotony is most important property of solutions of ordering optimization problems

    • Total sum of delays: optimal order is monotonic, BMI

    • Maximum delay: optimal order is monotonic, BMI

    • Optimization with crosstalk: optimal order is monotonic

    • Delay uncertainty optimization: optimal order is monotonic, BMI

  • Generally, all above problems can be solved on cyclic bus and obtained optimal order will be monotonic

  • BMI and other monotonic orders are special cases and defined by edge conditions only


Conclusions

  • Problem of optimal simultaneous wire sizing and ordering was presented and solved

  • Effects of crosstalk on nominal delays and delay uncertainty are examined

  • Monotonic ordering according to driver strength is shown to be advantageous for the various objective functions

  • Examples for 90-nanometer technology are analyzed and discussed


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