Report from cmos wg1
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Report from CMOS WG1. Interesting Foundries and State of Submissions Efficiency and Noise Occupancy Single Pixel Design Reticle Architectures Module Architectures Material Estimates Plans on how to proceed. Foundries. Extensive list of foundries discussed Five selected as most promising:

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Report from CMOS WG1

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Report from cmos wg1

Report from CMOS WG1

Interesting Foundries and State of Submissions

Efficiency and Noise Occupancy

Single Pixel Design

Reticle Architectures

Module Architectures

Material Estimates

Plans on how to proceed


Foundries

Foundries

  • Extensive list of foundries discussed

  • Five selected as most promising:

    • AMS 180 HV: Prototypes made and characterization underway

    • Global 130 HV: Prototypes made and characterization underway

    • Lfoundry 180 HR: Discussions/layout started; biasing structures designed

    • TowerJazz 180 HR: Good experience with foundry prototyping would be needed for biasing structure (radiation hardness). ALICE structures in hand for transistors/capacitors

    • EsprosPhotonics AG (EPC) 150 HR: Back bias structures available in design tools but collection diode is p-type in n-type. Some structures are available

  • We agreed radiation evaluation of 1-3 is of highest priority

    • TowerJazz had no current capabilities seen in addition to 1-3, but has good ties to RAL and CERN and excellent foundry

    • Esprosleast likely to be radiation tolerant.

  • For these 5 foundries, we agreed to talk with producers to flesh out summary talk with information about:

    • Expected charge collection (depletion depth, resistivity and thickness of EPII, max bias volt)

    • Cost (cost per wafer and expected yield)

    • Wafer Size (all 8”)

    • Availability of 1d stitching (in direction of hybrid in module, perp to strips)


Efficiency and noise occupancy

Efficiency and Noise Occupancy

  • We are using SCT 5×10-4 strip noise occupancy requirement (~5% of signal occupancy)

  • Minimum possible threshold set by noise floor (if noise is totally gaussian):

    • Threshold:Noise of 3.3:1 for strip, Threshold:Noise of 4.7:1 for a 50×74.5 mm2pixel element in a strip

  • In reality, minimum usablethreshold determined by non-gaussian effects (coherient)

    • For FEI3: T/N:~20:1

    • For FEI4: T/N:~10-12:1

    • For AMS180 HV: T:N:~15:1 but tuning could improve, hope to get to ~9:1

  • So for current AMS180 HV, minimum usable threshold is now 800 e- hoping to be reduced to 500-600 e-

  • From experience, a signal-to-threshold of 2.2:1 yield high efficiency (>99%) assuming uniform charge collection

  • For current AMS180 HV, the measured signal is much larger than expected (~1600-1900 e-)

    • Implies large diffusion component which might not be radiation hard

  • Even with larger charge, the devices currently have a S:T of 2-2.4:1

    • Past experience is that usable thresholds can more than double from single chips to full system

  • MORE WORK IS NEEDED TO:

    • DETERMINE SOURCE OF SIGNAL (TCT)

    • DETERMINE HOW SIGNAL BEHAVES WITH IRRADIATION

    • LOWER USABLE THRESHOLD

    • DESIGN TO IMPROVE THRESHOLD PERPFORMANCE

    • CHOOSE FOUNDRY (RESISTIVITY) TO TRY TO IMPROVE SIGNAL

LEDS TO DESIGN OPTIMIZATION WITH SIMPLEST POSSIBLE PIXEL


Single pixel geometry

Single Pixel Geometry

  • Collection Implant Capacitance, Threshold and Timing are correlated:

    • Smaller Capacitance -> Faster Timing ->Smaller Settable Threshold

  • Power, Threshold and Timing are also correlated

    • More power -> Faster Timing -> Smaller Settable Thresholds

  • To improve the Signal:Threshold, the collection diode geometry and the pixel power need to be optimized

    • We believe, for instance, doubling the FE power in the AMS 180 HV will give single bucket resolution

      • As a current stave can cool ~1 kW, we think we need to explore this

    • Current collection diodes are maximize to reduce non-uniformity of drift fields and to reduce collection distances

      • It may be possible to reduce the size (capacitance) but requires test beam (charged or focussed x-rays) after irradiation to prove uniformity of efficiency


Standard stereo

Standard Stereo

Connection of ending stereo strips

  • Minimal system would built-in stereo with current ABC130

    • Connect segments that end with corresponding strip on opposite side of reticle if no 1D stitching- uniform strip length

    • With 1d stitching would connect ending segments to those in next reticle

  • Hybrids and ABC130 only changed to provide servicing to CMOS periphery (init, power, …)

  • Active: 1.9 x 2.4 cm2 (matches 2 ABC130 – 256 x 74.5 wide)

  • Periphery:

    • ~>1% for init, powering, etc.

CMOS Periphery

NOT A PREFERRED SOLUTION. ANOTHER STEREO OPTION MAY HAVE LARGE PRODUCTION TIME AND NON CORE SAVINGS. ONLY USE IF SLIGHTLY MORE COMPLEX PERIPHERY AND ABC130 NOT POSSIBLE


Binary encoded stereo topology

“Binary-Encoded Stereo Topology”

Connection of ending stereo strips

  • Preferred stereo solution would be have a more advanced CMOS periphery and modified ABC130

    • Periphery would receive hit from active area and encode position as a 8 bit binary number

    • A hit strip would sent to ABC130 with 8 wire bonds -> a space point takes 16 wire bonds

      • 16 hit strips would take ½ of the FE wire bonds as current ABC130. Huge savings in build time and non-core costs

    • ABC130 analogue FE would be replaced with digital FE that receives the 8 bit strip locations and translates back into current ABC130 BE.

      • Francis believes this change is minimal and could occur in the “shadow” of the design study of the CMOS sensor

  • Hybrids are minimally changed

  • Active: 1.9 x 2.4 cm2 (matches 2 ABC130 – 256 x 74.5 wide)

  • Periphery:

    • ~3-5% for init, powering, etc and binary encoding

Binary Periphery

THIS OPTION CAN PROCEED WITH Managable DISRUPTION TO ASICs, DAQ, EOS, tapes, etc.


Digital z encoding sensor

“Digital Z-Encoding”- sensor

X

  • Digital Encoding of Z-info with ABC130 with “digital” pipeline

    • Active area is made up of separate z-segment connected to periphery either:

      • By a bussed structure (would be possible to confuse z position with 2 hits in one strip in one BC but finer granularity possible)

      • By dedicated lines back to periphery (z-segmentation set by minimum trace widths and spacing but no confusion possible in z)

    • Periphery would receive hit from active area and encode position as a M bit x position and N bit z position

      • For same number of bits as stereo space point (16), would reconstruct single pixel (74.5 x 50 micron2)

    • To recover current stereo resolution, a space point would need 12 bits (7 x and 5 z). A space point would sent to ABC130 with 12 wire bonds

      • 8 space points would take 1/3 of the FE wire bonds as current ABC130. Huge savings in build time and non-core costs

  • Active: 1.9 x 2.4 cm2 (matches 2 ABC130 – 256 x 74.5 wide)

  • Periphery:

    • ~3-5% for init, powering, etc and binary encoding

z

Digital Periphery


Digital z encoding asics

“Digital Z-Encoding”- ASICs

X

  • Digital Encoding of Z-info with ABC130 with “digital” pipeline

    • ABC130 analogue FE would be replaced with digital FE that receives the MxN bit z-encoded strip locations

    • ABC130 would then need a “digital” pipeline

      • Keeping to the current data buffer architecture, the size of the buffer would have to increase by (N+M-8) times; no feasible as data buffers are a significant fraction of the ABC130 size now

      • To keep to roughly the same size, would need to change to a data-driven pipeline.

  • Francis believes this change is significant and would require significant design time

    • To match onto CMOS sensor schedule for full-size submission, design would have to begin at beginning of 2015 with a design team of almost the same size

  • Would require either 2x the current ASIC design effort or delaying/cancelling final standard ABC130 in 2015

z

Digital Periphery

THIS OPTION CANNOT PROCEED WITHOUT MUCH DISRUPTION TO ASICs, DAQ, EOS, tapes, etc. REQUIRES HIGH CONFIDENCE IN CMOS SENSOR IN ~early 2015


Embedded cmos sensor

Embedded CMOS sensor

X

  • Finally, we could remove all wire bond connections between ABC130 and CMOS sensor by making it one piece

  • Requires digital ABC130 design and translation into CMOS sensor technology

    • Same work as making digital ABC130

  • Has huge benefits for assembly times and non-core costs

  • Hybrids simplified to just make connections between reticles and host HCC-like control chip

  • Could have significant cost and yield risks

    • Might make each wafer more expensive

    • Yield losses from sensor and ASIC added together

  • Periphery:

    • ~8 mm for embedded

z

“Embedded” ABC130 Periphery

REQUIRES SIGNIFICANT RESOURCES NOW. NOT CLEAR HOW TO EVALUATE COST AND YIELD RISK WITHOUT SIGNIFICANT PRODUCTION RUN


Discounted cmos architectures

Discounted CMOS Architectures

  • True drop-in (no z-info)

    • Not likely to actualize cost saving with respect to planar unless sensor area halved

    • Would require periphery on other edge in order to not have larger dead regions

  • Analogue z-encoding

    • It is strongly believed digital encoding is much easier to achieve both in the CMOS sensor and the ABC130


Outline of architecture program

Outline of architecture program

  • Proceed assume binary-encoded stereo topology

    • Francis will look more into changes needed for digital pipeline for ABC130

    • Renato will look at design of periphery option

    • Further evaluations of current CMOS devices

  • If CMOS still looks promising and additional z-resolution is useful:

    • Go to Digital Z-Encoding if both Francis’s and Renato’s studies are positive

    • If periphery looks to difficult, drop back to standard stereo

    • Else stay with binary-encoded stereo topology

  • Assume embedded CMOS is not within time constraints or financial resources unless schedule and funding changes really soon


Module architectures

Module Architectures

  • Not pursuing 2d stitching

    • Not possible at most foundries

    • Could have huge cost implications (cost per wafer and yield)

    • With 2d info in CMOS sensor, benefit of handling minimized

  • We assuming base module element will be a 4-5 reticle wide x 1 reticle long object

    • Might make sense to build modules out of two of these with peripheries pointing out

  • Width of base module element depends on how we assembly the reticle element and best use of the 8” wafers (current 97 mm width optimizes a 6” wafer)

  • Alternate modules on opposite sides of support material with overlapping active areas

Stave with alternating 48 mm modules


Low yield option i

“Low” Yield Option (I)

  • If yield is low (<90-95%), cost benefits will hard to achieve unless modules assembled out of single good reticles

    • Width of module independent of CMOS wafer size

  • Lowest mass method to do this is to use hybrid to tie reticles together

    • Required spacing between die and its precision isn’t obvious

  • In discussions with Tim, it may be more difficult to cool middle dies

    • No lateral cooling between dies (in silicon)

    • Cooling would have to be through face sheets to pipes


Low yield option ii

“Low” Yield Option (II)

  • A higher mass method would be to have a carrier with good thermal properties (CF, ceramics, TPG,..) which reticles are attached

  • Or you could extend hybrid flex to provide in-between option


Higher yield option

“Higher” Yield Option

  • If yield is higher (>90-95%), could dice reticles out into bigger sections.

    • Width of module would be set by best use of 8” CMOS wafer size

    • Have benefits for handling and thermal management

    • Hybrids could be done as now

  • If this option chosen, we will ask foundries if dead areas between reticles diced together can be minimized

    • For AMS and Lfoundry , it is ~80 microns dicing street with similar length between the last active element and the dicing street


1d stitching option option

1D stitching option Option

  • If available, 1d stitching could be considered

    • Benefits aren’t huge relative to dicing 1xn section of wafer

      • Periphery could be tied together which will make servicing CMOS sensor easier

    • For stereo option, stereo strips ending at each of reticle could be tied to neighboring reticle in a “continuous” line

    • Dead area between reticles could possibly be reduced


Radiation length

Radiation Length

  • Current radiation length of a stave

    • Cores (including tapes): 0.72%

    • 2 Planar Modules: 1.08%

    • Total: 1.8%

  • For CMOS assume no additional material in carrier

  • Drop-in Stereo and Z-Encoded (100 micron thick sensors):

    • 1 Drop-in Module: 0.31%

    • Total: 1.03%

  • Embedded (100 micron thick sensors + hybrid width reduced by ASIC size):

    • 1 Embedded Module: 0.25%

    • Total: 0.97%

It is possible that core can be reduced with CMOS sensors

Most of material improvement made with going to single modules with 2d information


Current priorities

Current Priorities

  • Determining the radiation tolerance of CMOS devices is of highest priority

    • AMS180 HV available now, imminent Lfoundry 150 HR submission important to explore higher resistivity material

    • It is not clear if this could be evaluated this year with current resources

    • It would be very useful if other groups could be involved

      • Requires FEI4 and USBPIX experience

  • Available test program

    • Source tests can be made to give relative efficiency vs bias voltage measurement (hit rate vs bias) and some measure of signal

    • Diamond at RAL could give focussed x-rays to give relative efficiency within a cell

    • Test beams are needed for absolute efficiencies

      • DESY has no available slots this year

      • SLAC may be available in May

      • CERN PS may be available in Oct

  • Lack of test beams in this years appears to be a (the) critical item in the CMOS program

Much more effort and resources are needed here to accelerate this evaluation. Without this ability, can not fulfil program in needed strip timescales


Schedule and resources

Schedule and Resources

  • CMOS program is still seen as a 3 submission program with (~>1 year per submission cycle)

    • Additional smaller submission might be needed to determine optimal pixel cell and power choices

    • This timing can only be achieved if things improve

      • Evaluation of new submissions limited by simulation/integration of large chips and support for readout of test structure (boards and DAQ)

        • Would be greatly improved if common powering, communication, layout, etc. was used in the different submissions

        • Having some analogue pixel cells as well as some with direct access to collection n-well would speed the irradiation evaluation of the new devices

      • Would greatly benefit with additional electrical engineering resources

  • ABC130 development for CMOS can wait about a year

    • To match CMOS program, a digital ABC130 layout would have to start in 2015

      • Work to understand if this is possible needs to happen now

    • A binary encoded system could wait for longer

  • The interaction between ABC130 for CMOS and ABC130 for planar will need understood/optimized/defined by the end of the year


New requests to wg2

New Requests to WG2

  • It would be useful to have the distribution of hit strips per ASIC as a function of pile up in dense jets

    • Would allow for more educated thinking of the needed number of output in the periphery


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