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Final Design Review of a 1 GHz LNA / Down-Converter. Charles Baylis University of South Florida April 22, 2005. LNA Design Summary. IBM SiGe Design Kit - 4 layers of metal Load resistance = 50 ohms (Filter)
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Final Design Review of a 1 GHz LNA / Down-Converter Charles Baylis University of South Florida April 22, 2005
LNA Design Summary • IBM SiGe Design Kit - 4 layers of metal • Load resistance = 50 ohms (Filter) • Feedback Resistor from collector to base stabilizes circuit, provides better matching • For feedback configuration • IC = 6 mA, RF = 460 ohms (initial – values were changed for final schematic.
LNA Design Summary • Power Consumption: Current through gain transistor + 1 mA reference current through current mirror. • LC Match on Input/Output • “De-Q” Inductors with resistors to improve bandwidth.
LNA Schematic Vcc 7.3 nH 1.4 kΩ 560 Ω 650 Ω 27 pF 4.5 pF Output 6.5 nH 9.3 pF 83 pF Input Ground
LNA Layout LNA Out LNA In Vcc
Mixer Design Approach • fRF = 1 GHz, fLO = 860 MHz, fIF = 140 MHz • Conversion gain = 9 dB = 2.82 • Output Resistance = 50 ΩRL= 25 Ω • Solve conversion gain equation for gm (gives starting value for current IC1).. • Use LC network for input matching.
Mixer Design Approach • Noise figure improved by shrinking reference transistor for current mirror (and associated current). Also, beta helper transistor size was increased. • As in LNA, “de-Q” inductors with shunt resistors to improve bandwidth.
Mixer Schematic Vcc 7.03 kΩ Out + Out - LO+ LO- 7 kΩ 7.8 nH Input 3.7 pF 83 pF 250 Ω Ground
Mixer Input/Output Match Input Reflection Coefficient Output Reflection Coefficient
Mixer Compliance Specified Gain and Bandwidth
Mixer Compliance - Temperature Specified Gain and Bandwidth
Mixer Compliance - Bias Specified Gain and Bandwidth
Mixer Layout Mixer In Vcc Out + Out - LO +- LO -
Conclusion • Only LNA noise figure does not meet specification at nominal temperature and bias. • Design has been run through multiple simulations to test its robustness.