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Developing test systems for multi-modules hardware designs

Developing test systems for multi-modules hardware designs. Mikhail Chupilko Institute for System Programming of RAS http://hardware.ispras.ru. Outline. Introduction How to perform hardware verification Single design under test case Plenty of designs under test case

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Developing test systems for multi-modules hardware designs

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  1. Developing test systems for multi-modules hardware designs Mikhail Chupilko Institute for System Programming of RAS http://hardware.ispras.ru

  2. Outline • Introduction • How to perform hardware verification • Single design under test case • Plenty of designs under test case • Results of the approach application • Conclusion

  3. Introduction Design Under Test MUT MUT Stimuli Reactions MUT MUT MUT MUT

  4. How to perform… • Formal approaches like Model checking • Simulation-based approaches mem_2p #(ADDR_SIZE,DATA_SIZE) mem( .DO(DO_tmp), .RD_A(RD_A), .WR_A(WR_A), .DI(DI_tmp), .RD_CLK(CLK), .WR_CLK(CLK), .CE_N_RD(~CE_RD_tmp), .CE_N_WR(~CE_WR_tmp), .OE_N(1'b0) ); always @(posedge CLK) begin if(RST) begin DO_VAL <= 1'b0; DO_R_VAL <= 1'b0; IS_EMPTY <= 1'b1; IS_R_FULL <= 1'b0; IS_RR_FULL <= 1'b0; SIMULATOR MUT

  5. Testbench elements SIMULATOR MUT Test Stimuli Generator Reaction Checker / Oracle Stimuli Reactions Information Test Completeness Estimator Information

  6. Approach: the common view

  7. Stimuli generator • Random-based generation • FSM-based generation A B State DUT C D

  8. Reaction checker

  9. Moving to multi-modules…

  10. Connected stimuli generators • Random-based generation • FSM-based generation State5 State2 A E State3 B F State7 MUT1 G C State6 State2 H D State1 State8 State3 State4 MUT2 State1 State4

  11. Connected reaction checkers

  12. Returning to the chip Design Under Test MUT MUT Stimuli Reactions MUT MUT MUT MUT

  13. Some results of the application

  14. Conclusions • The approach is applicable in hardware verification; • It supports both single modules as well as their unions.

  15. Thank you!Any questions?

  16. Open Verification Methodology OVC Master Slave Transaction System Generator Transaction System Generator Driver Monitor Driver Monitor Coverage Collector DUT

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