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한양대학교 박성주 교수

반도체 테스트 분야 산학협력 교육 및 연구. 한양대학교 박성주 교수. MORE accurate and fast !!!. Probe. Wafer. A T E. Handler. Chip. Index/cleaning time Relay DC/AC parameter BOST Prober Para (Memory/SoC). Defects -> Faults ATPG/Fault Simulation Design For X Scan (power) BIST etc. Channel BW SoC

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한양대학교 박성주 교수

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  1. 반도체 테스트 분야 산학협력 교육 및 연구 한양대학교 박성주 교수

  2. MOREaccurate and fast !!! Probe Wafer A T E Handler Chip Index/cleaning time Relay DC/AC parameter BOST Prober Para (Memory/SoC) • Defects -> Faults • ATPG/Fault Simulation • Design For X • Scan (power) • BIST • etc. Channel BW SoC Memory

  3. 반도체 테스트 관련 대학원 교과내용 • 고장 모델: Static/Dynamic • Automatic Test Pattern Generation • Fault Simulation • Ad Hoc Design for Testibility • Scan design • IEEE 1149.X & IEEE 1500 standards • Built-In Self-Test (Logic, Memory) • Memory Test (March 테스트, BISR 등) • 보충: ATE, Probe, Handler, DC parametric test • 보충: ATE-Probe-wafer 통합 관점에서 test cost 분석

  4. 반도체 테스트 분야 산학협력 (교육/연구) • 교육 • ATE architecture and function • Probe/Handler • Latest Industry Issues (seminar) • 연구 개발 • Probe + DFx • Handler + DFx • ATE +P/H + DFx • For TSV pre-bond/post-bond test

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