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Digital Design and System Implementation. Overview of Physical Implementations CMOS devices CMOS transistor circuit functional behavior Basic logic gates Transmission gates Tri-state buffers Flip-flops vs. latches revisited. Overview of Physical Implementations.

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Digital design and system implementation
Digital Design and System Implementation

  • Overview of Physical Implementations

  • CMOS devices

  • CMOS transistor circuit functional behavior

    • Basic logic gates

    • Transmission gates

    • Tri-state buffers

    • Flip-flops vs. latches revisited

CS 150 – Spring 2007 - Lec #26 – Digital Design – 1


Overview of physical implementations
Overview of Physical Implementations

The stuff out of which we make systems

  • Integrated Circuits (ICs)

    • Combinational logic circuits, memory elements, analog interfaces

  • Printed Circuits (PC) boards

    • substrate for ICs and interconnection, distribution of CLK, Vdd, and GND signals, heat dissipation

  • Power Supplies

    • Converts line AC voltage to regulated DC low voltage levels

  • Chassis (rack, card case, ...)

  • 1-25 conductive layers

    • holds boards, power supply, fans, provides physical interface to user or other systems

  • Connectors and Cables

CS 150 – Spring 2007 - Lec #26 – Digital Design – 2


Integrated circuits

Primarily Crystalline Silicon

1mm - 25mm on a side

200 - 400M effective transistors

(50 - 75M “logic gates")

3 - 10 conductive layers

2007 feature size ~ 65nm = 0.065 x 10-6 m45nm coming on line

“CMOS” most common - complementary metal oxide semiconductor

Chip in Package

Integrated Circuits

  • Package provides:

    • Spreading of chip-level signal paths to board-level

    • Heat dissipation.

  • Ceramic or plastic with gold wires

CS 150 – Spring 2007 - Lec #26 – Digital Design – 3


Printed circuit boards

Multichip Modules (MCMs)

  • Multiple chips directly connected to a substrate (silicon, ceramic, plastic, fiberglass) without chip packages

Printed Circuit Boards

  • Fiberglass or ceramic

  • 1-20in on a side

  • IC packages are soldered down

CS 150 – Spring 2007 - Lec #26 – Digital Design – 4


Integrated circuits1
Integrated Circuits

  • Moore’s Law has fueled innovation for the last 3 decades

  • “Number of transistors on a die doubles every 18 months.”

  • What are the consequences of Moore’s law?

CS 150 – Spring 2007 - Lec #26 – Digital Design – 5


Integrated circuits2
Integrated Circuits

  • Uses for Digital IC technology today:

    • Standard microprocessors

      • Used in desktop PCs, and embedded applications (ex: automotive)

      • Simple system design (mostly software development)

    • Memory chips (DRAM, SRAM)

    • Application specific ICs (ASICs)

      • custom designed to match particular application

      • can be optimized for low-power, low-cost, high-performance

      • high-design cost / relatively low manufacturing cost

    • Field programmable logic devices (FPGAs, CPLDs)

      • customized to particular application after fabrication

      • short time to market

      • relatively high part cost

    • Standardized low-density components

      • still manufactured for compatibility with older system designs

CS 150 – Spring 2007 - Lec #26 – Digital Design – 6


Cmos devices

Cross Section

The gate acts like a capacitor. A high voltage on the gate attracts charge into the channel. If a voltage exists between the source and drain a current will flow. In its simplest approximation, the device acts like a switch.

CMOS Devices

  • MOSFET (Metal Oxide Semiconductor Field Effect Transistor)

Top View

nFET

pFET

CS 150 – Spring 2007 - Lec #26 – Digital Design – 7


Logic and layout nand gate
Logic and Layout: NAND Gate

CS 150 – Spring 2007 - Lec #26 – Digital Design – 11


Transmission gate

Transmission gates are the way to build “switches” in CMOS

In general, both transistor types are needed:

nFET to pass zeros

pFET to pass ones

The transmission gate is bi-directional (unlike logic gates)

Does not directly connect to Vdd and GND, but can be combined with logic gates or buffers to simplify many logic structures

Transmission Gate

CS 150 – Spring 2007 - Lec #26 – Digital Design – 12


Pass transistor multiplexer

2-to-1 multiplexer: CMOS

c = sa + s’b

Switches simplify the implementation:

Pass-Transistor Multiplexer

s

a

c

s’

b

CS 150 – Spring 2007 - Lec #26 – Digital Design – 13


4 to 1 pass transistor mux

The series connection of pass-transistors in each branch effectively forms the AND of s1 and s0 (or their complement)

20 transistors

4-to-1 Pass-transistor Mux

CS 150 – Spring 2007 - Lec #26 – Digital Design – 14


Alternative 4 to 1 multiplexer

This version has less delay from in to out effectively forms the AND of s1 and s0 (or their complement)

Care must be taken to avoid turning on multiple paths simultaneously (shorting together the inputs)

36 Transistors

Alternative 4-to-1 Multiplexer

CS 150 – Spring 2007 - Lec #26 – Digital Design – 15


Example tally circuit
Example: Tally Circuit effectively forms the AND of s1 and s0 (or their complement)

N inputs: How many of these are asserted?

N

Two

One

Zero

Tally

In

I1

E.g., 1 input, 2 outputs: One, Zero

E.g., 2 inputs, 3 outputs: Two, One, Zero

N inputs, N+1 outputs: N, …, One, Zero

CS 150 – Spring 2007 - Lec #26 – Digital Design – 16


Example tally circuit1

1 effectively forms the AND of s1 and s0 (or their complement)

0

Example: Tally Circuit

CS 150 – Spring 2007 - Lec #26 – Digital Design – 17


Example tally circuit2
Example: Tally Circuit effectively forms the AND of s1 and s0 (or their complement)

CS 150 – Spring 2007 - Lec #26 – Digital Design – 18


Example tally circuit3
Example: Tally Circuit effectively forms the AND of s1 and s0 (or their complement)

CS 150 – Spring 2007 - Lec #26 – Digital Design – 19


Example tally circuit4
Example: Tally Circuit effectively forms the AND of s1 and s0 (or their complement)

2 inputs, 3 outputs:

Two, One, Zero

I1

0

1

1

0

CS 150 – Spring 2007 - Lec #26 – Digital Design – 20


Example tally circuit5
Example: Tally Circuit effectively forms the AND of s1 and s0 (or their complement)

2 inputs, 3 outputs:

Two, One, Zero

I1

0

1

0

CS 150 – Spring 2007 - Lec #26 – Digital Design – 21


Example tally circuit6
Example: Tally Circuit effectively forms the AND of s1 and s0 (or their complement)

2 inputs, 3 outputs:

Two, One, Zero

CS 150 – Spring 2007 - Lec #26 – Digital Design – 22


Example tally circuit7
Example: Tally Circuit effectively forms the AND of s1 and s0 (or their complement)

2 inputs, 3 outputs:

Two, One, Zero

CS 150 – Spring 2007 - Lec #26 – Digital Design – 23


Example tally circuit8
Example: Tally Circuit effectively forms the AND of s1 and s0 (or their complement)

2 inputs, 3 outputs:

Two, One, Zero

CS 150 – Spring 2007 - Lec #26 – Digital Design – 24


Example tally circuit9
Example: Tally Circuit effectively forms the AND of s1 and s0 (or their complement)

2 inputs, 3 outputs:

Two, One, Zero

CS 150 – Spring 2007 - Lec #26 – Digital Design – 25


Example crossbar switch
Example: Crossbar Switch effectively forms the AND of s1 and s0 (or their complement)

N inputs, N outputs, N x N control signals

Cross

Bar

Outi

Busi

Note: circuit like this

used inside Xilinx

switching matrix

CS 150 – Spring 2007 - Lec #26 – Digital Design – 26


Barrel shifter
Barrel Shifter effectively forms the AND of s1 and s0 (or their complement)

Barrel

Shifter

Bus

Out

Shift

Bus Shift

CS 150 – Spring 2007 - Lec #26 – Digital Design – 27


Example barrel shifter

Shift 0 effectively forms the AND of s1 and s0 (or their complement)

Example: Barrel Shifter

N inputs, N outputs, N control signals

CS 150 – Spring 2007 - Lec #26 – Digital Design – 28


Example barrel shifter1

Shift 1 effectively forms the AND of s1 and s0 (or their complement)

Example: Barrel Shifter

N inputs, N outputs, N control signals

CS 150 – Spring 2007 - Lec #26 – Digital Design – 29


Example barrel shifter2
Example: Barrel Shifter effectively forms the AND of s1 and s0 (or their complement)

N inputs, N outputs, N control signals

Rotating

Shift 1

CS 150 – Spring 2007 - Lec #26 – Digital Design – 30


Tri state based multiplexer

Multiplexer effectively forms the AND of s1 and s0 (or their complement)

If s=1 then c=a else c=b

Transistor Circuit for inverting multiplexer:

Tri-state Based Multiplexer

CS 150 – Spring 2007 - Lec #26 – Digital Design – 33


D type edge triggered flip flop

The edge of the clock is used to effectively forms the AND of s1 and s0 (or their complement)sample the "D" input & send it to "Q” (positive edge triggering)

At all other times the output Q is independent of the input D (just stores previously sampled value)

The input must be stable for a short time before the clock edge.

D-type Edge-triggered Flip-flop

CS 150 – Spring 2007 - Lec #26 – Digital Design – 34


Transistor level logic circuits

Positive Level-sensitive effectively forms the AND of s1 and s0 (or their complement)latch:

Latch Transistor Level:

Positive Edge-triggered flip-flop built from two level-sensitive latches:

Transistor-level Logic Circuits

clk’

clk’

clk

clk

CS 150 – Spring 2007 - Lec #26 – Digital Design – 35


State machines in cmos
State Machines in CMOS effectively forms the AND of s1 and s0 (or their complement)

  • Two Phase Non-Overlapping Clocking

P2

P1

Out

In

R

E

G

R

E

G

Combinational

Logic

1/2 Register

1/2 Register

State

CLK

P1

P2

CS 150 – Spring 2007 - Lec #26 – Digital Design – 36


Digital design and implementation summary
Digital Design and Implementation Summary effectively forms the AND of s1 and s0 (or their complement)

  • CMOS preferred implementation technology

  • Much more than simple logic gates

    • Transmission gate as a building block

    • Used to construct “steering logic”

    • Very efficient compact implementations of interconnection and shifting functions

  • Simple storage building blocks

    • D-type flip flop behavior with cross-coupled inverters and two phase clocking

  • Heart of Xilinx implementation structures

CS 150 – Spring 2007 - Lec #26 – Digital Design – 37


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