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Verification of Reconfigurable Binary Decision Diagram-based Single Electron Transistor Arrays

Speaker: Li-Fu Tang Advisor: Dr. Chun-Yao Wang 2012/6/22. Verification of Reconfigurable Binary Decision Diagram-based Single Electron Transistor Arrays. Out line. Introduction Main Algorithm CNF model CNF transformation Overall verification flow Issues of applying to our approach

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Verification of Reconfigurable Binary Decision Diagram-based Single Electron Transistor Arrays

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  1. Speaker: Li-Fu Tang Advisor: Dr. Chun-Yao Wang 2012/6/22 Verification of Reconfigurable Binary Decision Diagram-based Single Electron Transistor Arrays

  2. Out line • Introduction • Main Algorithm • CNF model • CNF transformation • Overall verification flow • Issues of applying to our approach • Experimental result • Future work

  3. Mapping constraint • Fabric constraint • The combination of n.left and n.right, (n.left,n.right), must be one of (high, low), (low, high), (short, short),and (open, open), where n is a node in the SET array. • (high, low) and (low, high) cannot simultaneously appear in a row • For simplification, we allow only one of (high, low) and (low, high) to appear in an SET array 0110 0102 1122

  4. Existential quantification • The existential quantification is an operator that existentially quantifies away a variable x from f to obtain a Boolean function • Example

  5. Problem formulation • Given: A mapped SET array with fabric constraint and its specificationrepresented as a Boolean circuit • Objective: Verify their functional equivalence

  6. Out line • Introduction • Main Algorithm • CNF model • CNF transformation • Overall verification flow • Issues of applying to our approach • Experimental result • Future work

  7. Key Ideas • Transfer the SET array into Boolean circuit • SET array is composed of a set of configured edges that determine functionality • Model each configured edge as a CNF, and collect all the CNFs and merge them • SET array => CNF => Boolean circuit

  8. CNF Model(1/4) • Active High • x = 1, edge is conducting, nt= nd • nt≠ nd, edge is non-conducting, x = 0 nt x nd

  9. CNF Model(2/4) • Active Low • x = 0, edge is conducting, nt= nd • nt≠ nd, edge is non-conducting, x = 1 nt ~x nd

  10. CNF Model(3/4) • Short • ntand ndalways have the same logical value nt nd

  11. CNF Model(4/4) • Open • No CNF model because ntand ndhave no direct logical relationship nt nd No CNF model

  12. Example of complete CNF a b

  13. CNF transformation • After constructing the CNF for an SET array, we can transform it into a Boolean function based on the relationship of nodes and variables • In order to represent whole SET array, we need to define the clause of current source and current detector and add them into the complete CNF

  14. Construct whole CNF • Suppose the current source is represented as a logical value 1, if n0_0 has a logical value 0, there must be no conducting path • We can’t set both of them as 1 to obtain all conducting path due to the open edge • Instead, we can add corresponding clause to obtain the off-set of SET array

  15. Example a b

  16. CNF transformation(1/2) • We do not actually compute all the solutions, and collect them as the off-set for constructing Boolean function • The complete CNF can be considered as another Boolean function f • Existentially quantify away all the variables of f that are not corresponding to the control variables, and obtain a new Boolean function f’

  17. Example

  18. CNF transformation(2/2) • The Boolean function of on-set can be obtained by negate f’ • We can verify whether the obtained Boolean function meets the given Boolean function (specification)

  19. Overall verification flow

  20. Out line • Introduction • Main Algorithm • CNF model • CNF transformation • Overall verification flow • Issues of applying to our approach • Experimental result • Future work

  21. Example 01001 00221 11221 10001 10121 10100 11000 10022 11012 11122

  22. Issues about our approach • Redundant edges due to fabric constraint • They don’t connect to the bottom • They make the CNF larger and gain more effort on existential quantification • Not every nodes in the bottom connect to current source • Different variable ordering

  23. Redundant edges 01001 00221 11221 10001 10121 10100 11000 10022 11012 11122

  24. Justify the redundant edges • Property of redundant edges • The edge doesn’t connect any lower level edges • The edge is not the start point of expansion • Justify the redundant edges when generate the CNF, and avoid generate the CNF of redundant edges

  25. Modifications • Mark the nodes connect to the current source • Use the new variable ordering to construct CNF of SET array • Justify the redundant edges for speed up

  26. Out line • Introduction • Main Algorithm • CNF model • CNF transformation • Overall verification flow • Issues of applying to our approach • Experimental result • Future work

  27. Experimental results • Platform • Workstation of CSIE • Experiment • 13 benchmark from MCNC • BDD-based & LTG-based mapping results • All correct

  28. Experimental results

  29. Out line • Introduction • Main Algorithm • CNF model • CNF transformation • Overall verification flow • Issues of applying to our approach • Experimental result • Future work

  30. Future work • Head for JETC • Conduct more experiment • Paper writing

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