Principle behind hierarchical storage
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Principle Behind Hierarchical Storage. Each level memorizes values stored at lower levels Instead of paying the full latency for the “furthermost” level of storage each time Effective Access T i = h i • t i + (1 - h i ) • T i+1

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Principle Behind Hierarchical Storage

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Principle behind hierarchical storage

Principle Behind Hierarchical Storage

  • Each level memorizes values stored at lower levels

  • Instead of paying the full latency for the “furthermost” level of storage each time

    Effective Access Ti = hi• ti + (1 - hi)•Ti+1

    • where hi is the ‘hit’ ratio, the probability of finding the desired data memoized at level i

    • ti is the raw access time of memory at level i

  • Given a program with good locality of reference

    Sworking-set < si hi1  Titi

  • A balanced system achieves the best of both worlds

    • the performance of higher-level storage

    • the capacity of lower-level low-cost storage.

    • Assumption: faster memory is more expensive


    Caching vs demand paging

    primary

    memory

    Caching vs Demand Paging

    secondary

    memory

    primary

    memory

    CPU

    CPU

    cache

    cachingdemand paging

    cache entrypage-frame

    cache block (~16 bytes)page (~4k bytes)

    cache miss (1% to 20%)page miss (~.001%)

    cache hit (~1 cycle)page hit (~10 cycles)

    cache miss (~10 cycles)page miss(~10K cycles)

    a miss is handled in a miss is handled mostly in

    hardwaresoftware


    Modern virtual memory systems illusion of a large private uniform store

    VA

    PA

    map

    -ping

    Swapping

    Store

    Primary

    Memory

    Modern Virtual Memory Systems:illusion of a large, private, uniform store

    Demand Paging

    capacity of secondary memory

    at the speed of primary memory

    Address Translation

    dynamic relocation

    large “perceived” address space

    Protection

    several users, each with their private

    address space and a common system

    space

    OS

    useri


    Virtual to physical address translation

    Virtual to Physical Address Translation

    Virtual Address

    Main Memory

    PA = f(VA)

    decoder

    Physical Address

    Swap Disk


    Page based virtual memory

    Virtual address

    (64-bit)

    Page offset

    (12-bit)

    (1~10 GBytes)

    Virtual page number

    Main memory pages

    Translation memory (page table)

    decoder

    (52-bit)

    (~8-bytes)

    decoder

    Physical Page Number

    Physical address

    (40-bit)

    (10 ~ 100 GBytes)

    Where to hold this translation memory and how much translation memory do we need?

    Page-Based Virtual Memory


    Hierarchical page table

    12-bit

    10-bit

    10-bit

    p1 p2 P.O.

    effective address

    processor

    register

    p2

    p1

    Base of the Page Table of the page tables

    d

    Page Table of

    the page tables

    pages of the

    page table

    page in secondary memory

    page in primary memory

    page does not exist

    pages

    Hierarchical Page Table

    Storage of overhead of translation should be proportional to

    the size of physical memory and not the virtual address space


    Inverted page tables

    Inverted Page Tables

    Inverted

    Page Table

    Base of Table

    Table

    Offset

    PID

    PA of IPTE

    +

    hash

    VPN PID PTE

    VPN

    Size of Inverted Page table only needs to be

    proportional to the size of the physical memory

    Each VPN can only be mapped to a small set

    of entries according to a hash function

    To translate a VPN, check all allowed table entries for matching VPN and PID

    Physical

    Memory

    How many memory lookup per translation?


    Translation look aside buffer tlb

    Translation Look-aside Buffer (TLB)

    Virtual address

    Virtual page no.

    Page offset

    Tag

    =

    Index

    Page offset

    Physical page no.

    Physical address

    A cache of address translations


    Set associative and fully associative tlbs

    tag

    page offset

    Virtual page no.

    PPN tag

    =

    =

    =

    Page offset

    =

    Phy. pg. no.

    Physical address

    Set-Associative and Fully Associative TLBs

    Virtual page no.

    tag idx

    page offset

    PPN tag

    =

    =

    Page offset

    Phy. pg. no.

    Physical address

    What are relative sizes of ITLB, BTB and I-cache?


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