Object Oriented HW/SW System Design with SystemC and OSSS

1. Object Oriented HW/SW System Designwith SystemC and OSSS Objective Systems Solutions Christian Stehno OFFIS – Institute for Information Technology HW/SW Design Methodology Group Oldenburg, Germany

2. Outline Motivation Why do we need improvements towards ESL/HLS Introduction ESL/HLS SystemC Design Process Design and Simulation Library OSSS Features and Advantages Example on Communication exploration Synthesis tool FOSSY Features and Advantages Example on IP core integration Conclusion

3. Motivation Embedded Systems are ubiquitous, and so is their design Today's design techniques have matured over decadesbut without major structural changes Hence, highly specialized skills are required, costs and time are always too high Compared to SW engineering advancements, HW design is far behind But, new technologies and methodologies are arising Electronic System Level lifts the abstraction level High Level Synthesis closes the gap from abstraction to realization SysML, System Verilog, and SystemC make use of SE techniques and provide means for enhanced design processes New generations of design tools show up

4. Introduction Electronic System Level (ESL) Increase the level of abstraction of the initial models of a system Thereby improve the comprehensibility of the design Introduce new tools and modeling languages HLS, SysML, SystemC, … High Level Synthesis (HLS) The missing link from models to hardware Automatic transformation from high-level languages into HDL Establish seamless development Distinction based on the performed steps Behavioral synthesis Algorithmic synthesis

5. SystemC Modeling and simulation class library for system-level design Standardized as IEEE 1666-2005, promoted by the OSCI Historically derived from VHDL with emphasis on RTL Provides structures and hierarchy for system modeling Simulation kernel based on the executable semantics Concurrency simulated via pseudo parallel delta-cycle semantics Foundations in C++ provide a rich data type pool and strong expressiveness Communication is method based, using ports, interfaces, channels, and signals Transaction-Level Modeling (TLM) improves simulation performance and early explorations on the virtual prototype

6. #include "systemc.h" SC_MODULE(dff) { sc_in<bool> din; sc_in<bool> clock; sc_out<bool> dout; void doit(){ dout = !din; } SC_CTOR(dff){ SC_METHOD(doit); sensitive_pos << clock; } }; SystemC Example Inverting D FlipFlop example SC_MODULE defines structure, encapsulates strongly related tasks sc_in and sc_out define ports for connections into and out of this module Method doit is declared as SC_METHOD with sensitivity on the clock portHence, on each clock high signal the doit method copies the in-signal to the out-port

7. Design flow The proposed design methodology resembles the typical ESL process: Functional modeling in SystemC/C++ Refinement towards synthesizability HLS into HDL Logic synthesis in the backend System verification is possible before and after synthesis in SystemC SystemC/C++ Design Simulation & Verification FOSSY RTL IP Xilinx EDK VHDL SystemC RTL Synthesis (e.g. Xilinx ISE)

8. Design process

9. Design process C++ (golden) model Algorithmic specification Fully functional implementation of the reactive and/or computational part Partitioned/refined into SystemC based virtual system prototype Partitioned into independent processes and communication links As much as possible without any link to the actual platform Abstractions of actual HW yield simulation performance and enable large exploration spaces C++ Model Application Layer

10. Design process Exploration and refinement yield Dedicated, yet technology-unaware architecture Communication-driven optimization towards final partition and HW/SW interfaces Timing is refined by explicit clock boundaries Mapping results in Platform specific IP cores Pin-accurate communication interfaces Transactor introduction Fully synthesizable, cycle accurate model Bus SW Processor HW Block HW Block HW Block HW Block Bus µP/µC Bus IF RAM Virtual Target Architecture Layer Target Platform

11. Design process Synthesis into simplified RTL code Removal of OO Optimization FSM synthesis Signal level interface generation VHDL code generation for logic synthesis Optimizations based on chosen platform Actual IP core instantiation Backend script generation SystemC code generation for post-synthesis simulation without co-simulation Synthesizer FOSSY VHDL SystemC

12. Design and Simulation Library OSSS Object-oriented extension for SystemC, developed at OFFIS Additional primitive blocks for convenience, simulation speed, and optimal synthesis results FIFOs, RAMs, ROMs Full C++ data type support including used-defined classes Requires serialization techniques for signal decomposition Provides inheritance, overloading, and polymorphism for increased re-use Templates allow for efficient and concise designs SW tasks for processor executed processes Very similar to SystemC modules, but certain restrictions OS effects, such as scheduling, can be simulated Timing is abstracted for simulation performance by Estimated Execution Timesand Required ETs on the block level

13. Design and Simulation Library OSSS Shared Objects Very general communication and synchronization element Shared between multiple processes Allow for HW/HW, HW/SW and SW/SW communication Guarded methods for mutual exclusion measures,e.g. as semaphore or monitor Useable as shared resource or high-level container Method calls can be mapped to arbitrary communication channels OSSS library and simulator (SystemC) available for freehttp://www.system-synthesis.org

14. template<class ItemType> class put_if : public sc_interface { public: virtual void put(ItemType item) = 0; virtual bool is_empty() = 0; virtual bool is_full() = 0; ... }; template<class ItemType> class get_if : public sc_interface { public: virtual ItemType get() = 0; virtual bool is_empty() = 0; virtual bool is_full() = 0; ... }; <<implements>> <<implements>> Shared Object Example Producer-Consumer Consumer Producer osss_port<get_if<Packet>> osss_shared<rendezvous_channel<Packet>, osss_round_robin> osss_port<put_if<Packet>>

15. Communication Mapping Alternatives (VTA 1) Interface Port Application OPB Software Processor Hardware Block Virtual Target Architecture Object Socket Hardware Block Shared Bus Topology Point-to-Point Topology

16. Communication Mapping Alternatives (VTA 2) Interface Port Application OPB Software Processor Hardware Block Virtual Target Architecture Object Socket Hardware Block Shared Bus Topology

17. OPB Xilinx MicroBlaze Hardware Block Hardware Partition Object Socket Hardware Block Software Partition VHDL C++ VHDL Xilinx EDK project C++ driver lib VHDL C++ from Xilinx IP core library OPB Xilinx MicroBlaze Synthesised Consumer Synthesised Shared Object OPB IF OPB DDR Controller DDR RAM Synthesised Consumer FOSSY generated OPB Arbiter e.g. Xilinx ML401 FPGA prototyping board Synthesis Flow Board Support Package OSSS Flow OSSS Design Xilinx IP Lib Xilinx EDK 3rd party tools gcc linker

18. High Level Synthesis Translation of synthesizable models into target code VHDL for logic synthesis SystemC for post-synthesis simulation Resolution of object-oriented features Implementation according to the language semantics Strong semantics equivalence Implicit state machine synthesis Optimization Loop unrolling Function inlining Code fragment recognition Predictability and Traceability Synthesized code resembles the high-level model

19. High Level Synthesis HW/SW separation Cross compilation of SW modules SW processor implementation defines deployment Platform description generated for certain backend tools Communication elements Transactor synthesis for module interfacing Channel synthesis via IP cores or user-defined synthesizable protocols (Legacy) IP core integration SystemC wrapper for co-simulation Synthesis through replacement by HDL core Also happening for certain OSSS primitives depending on parameters and platform type chosen

20. Video Filter running on Xilinx FPGA prototyping boardIP core generation and integration

21. Algorithmic Design top video_source video_sink filter_top test.bmp test_out.bmp filter_ inner chunk_ buffer filter_synth.cc filter_golden.cc

22. Integration into existing architecture VDEC1 Board XUP-V2Pro Development System Analog INTERLACED Video Video Timing Extraction Create the missing Chroma data samples Color Space Conversion Digital Video 4:2:2 YCrCb 4:4:4 YCrCb 4:2:2 to 4:4:4 Conversion YCrCb to RGB Conversion 4:4:4 RGB Video Decoder Line Field Decoder CCIR 601/656 YCrCb Data Format Composite (YPrPb) Video Timing Generation Logic Line Buffer (BRAM) Select the ACTIVE LINE BUFFER for WRITES @ 13.5MHz Buffer Control Logic Select the ACTIVE LINE BUFFER for READS @ 27MHz Hsync Vsync Blanking Pixel Clock Line Buffer (BRAM) 24 Bit RGB Video Data Analog PROGRESSIVE Video filter_top Video DAC 720 x 480 @ 60Hz DE-INTERLACE by LINE DOUBLING filter_synth.vhd

23. Simulation/Test SystemC Testbench SystemC g++ test.bmp run.x test_out.bmp The whole design flow filter.h includes filter.cpp Synthesis systemc_synth.h synthesised_filter.vhd synthesised_filter.cc Xilinx XST, Synopsys Synplify Pro, etc. 3rd party RTL synthesis tools

24. Conclusion The proposed OSSS design process shows major advantages Strict separation of application, architecture, and platform Flexible communication means Simple IP integration A seamless C++/SystemC design process with end-to-end simulation, automatic synthesis, all in one IDE Available to all kinds of developers, from SW to HW engineers The future tasks Broader support for transactor synthesis Enhanced simulation modes More behavioral synthesis elements

25. Objective Systems Solutions SystemC C++ FOSSY Live Demo @ www.system-synthesis.org