1 / 27

Verilog Synthesis & FSMs

Learn about Verilog synthesis and finite state machines (FSMs) in this lab lecture. Topics include designing digital logic, efficient hardware design, HDL simulation, blocking vs. non-blocking, administrative information, and implementing a combo lock.

leond
Download Presentation

Verilog Synthesis & FSMs

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript


  1. Verilog Synthesis & FSMs EECS150 Fall2008 - Lab Lecture #3 IliaLebedev Adopted from slides designed by Greg Gibeling EECS150 Lab Lecture #3

  2. Today • Designing Digital Logic • Efficient Hardware Design • HDL Simulation • Blocking vs. Non-Blocking (revisited) • Administrative Info • Lab #3: The Combo Lock • FSMs in Verilog EECS150 Lab Lecture #3

  3. Designing Digital Logic (1) • High Level Design • Top Down Design • Partitioning & Interfaces • Implementing the Design • Follow the flow of data • Start with Inputs • Determine State • Generate Outputs EECS150 Lab Lecture #3

  4. Designing Digital Logic (2) • Start with Inputs • What are they? • Possible Values • Timing • Process Them • Raw inputs are often not what you need • Might need delay/timing change • Might look for a specific value/range EECS150 Lab Lecture #3

  5. Designing Digital Logic (3) • Determine State • What does the module need to remember? • Has it seen a particular input • How many cycles have passed • Design Memory for State • Generalized FSM • Standard D Register • Counter • Shift Register EECS150 Lab Lecture #3

  6. Designing Digital Logic (4) • Generate Outputs • What are they? • Possible Values • Timing • Create the outputs • Don’t set them, they’re not variables • Compute them from state (and inputs) • Learn to think in Boolean equations • assign is your friend EECS150 Lab Lecture #3

  7. Efficient Hardware Design (1) always @ (*) begin if (a) Z = A + B; else Z = A + C; end always @ (*) begin if (a) aux =B; else aux = C; Z = A + aux; end EECS150 Lab Lecture #3

  8. Efficient Hardware Design (2) assign B = 3; assign Z = A * B; assign Z = A + (2 * A); assign Z = A + (A << 1); assign Z = A + {A, 1’b0}; EECS150 Lab Lecture #3

  9. Efficient Hardware Design (3) assign aux = A + {1’b0, A[n-1:1]}; assign Z = {aux, A[0]}; EECS150 Lab Lecture #3

  10. HDL Simulation (1) • Software Based Simulation • Fast, simple and accurate • Allows for simulation at any precision • Easy to see any signal • Perfect Visibility • Drawbacks • Simulator Dependant • Deadlocks are Possible! • Simulation != Synthesis EECS150 Lab Lecture #3

  11. HDL Simulation (2) • Event Driven Simulation • Maintain a queue of events • Pull next event off the queue • Determine its consequences • Add more events to the queue • Implications • Verilog is not executed! • Things don’t necessarily happen in order • Verilog is SIMULATED EECS150 Lab Lecture #3

  12. Blocking vs. Non-Blocking revisited (1) Verilog Fragment Result always @ ( * ) begin b = a; c = b; end C = B = A always @ (posedge Clock) begin b <= a; c <= b; end B = Old A C = Old B EECS150 Lab Lecture #3

  13. Blocking vs. Non-Blocking revisited (2) • Use Non-Blocking for FlipFlop Inference • posedge/negedge require Non-Blocking • Else simulation and synthesis wont match • Use #1 to show causality always @ (posedge Clock) begin b <= #1 a; c <= #1 b; end EECS150 Lab Lecture #3

  14. Administrative Info • Lab Policy • Getting Help with Verilog • Card Keys • Webcast (again) EECS150 Lab Lecture #3

  15. Kramnik • Terminal Server • Currently has old tools. Update soon. • Log in from off campus • Run simulations • Transfer files • How-To • Its pretty easy • http://www-inst.eecs.berkeley.edu/~cs150/sp05/Kramnik.htm EECS150 Lab Lecture #3

  16. Lab #3: The Combo Lock (1) • Used to control entry to a locked room 2bit, 2 digit combo (By Default 11, 01) Set code to 11, Press Enter Set code to 01, Press Enter Lock Opens (Open = 1) EECS150 Lab Lecture #3

  17. Lab #3: The Combo Lock (2) EECS150 Lab Lecture #3

  18. Lab #3: The Combo Lock (3) • Example 1: • 1: Press ResetCombo, Combo: 2’b11, 2’b01 • 2: Set 2’b11, Press Enter • 3: Set 2’b01, Press Enter, LEDs: “OPEN” • 4: Press Enter, LEDs: “Prog1” • 5: Set 2’b00, Press Enter, LEDs: “Prog2” • 6: Set 2’b10, Press Enter, LEDs: “OPEN” • 7: Combo: 2’b00, 2’b10 EECS150 Lab Lecture #3

  19. Lab #3: The Combo Lock (4) • Example 2: • 1: Press ResetCombo, Combo: 2’b11, 2’b01 • 2: Set 2’b01, Press Enter • 3: Set 2’b01, Press Enter, LEDs: “Error” • Why doesn’t “Error” show until step 3? EECS150 Lab Lecture #3

  20. Lab #3: The Combo Lock (5) EECS150 Lab Lecture #3

  21. Lab #3: The Combo Lock (6) EECS150 Lab Lecture #3

  22. Lab #3: The Combo Lock (7) • Debugging with LEDs • A powerful way to debug • Easy to understand • Lower overhead than other debugging tools • A great way to see NextState/CurrentState • Drawbacks • Slow, can’t see fast events • No timing information, no waveform • Limited number • Dipswitches! EECS150 Lab Lecture #3

  23. FSMs in Verilog (1) • Mealy Machines • Output based on input and state • Can have major timing problems • Moore Machines • Output based on current state • Easier to work with • Slightly harder to build Mealy Machine Moore Machine EECS150 Lab Lecture #3

  24. FSMs in Verilog (2) • Two always blocks • 1st: CurrentState Register • Clocked • Handles Reset • 2nd: Generates NextState • Uses CurrentState and Inputs • Combinational • Generate Outputs • Use CurrentState only • Use assigns EECS150 Lab Lecture #3

  25. FSMs in Verilog (3) module MyFSM(In, Out, Clock, Reset); input In, Clock, Reset; output Out; parameter STATE_Idle = 1’b0, STATE_Run = 1’b1; STATE_X = 1’bx; reg CurrentState, NextState, Out; always @ (posedge Clock) begin if (Reset) CurrentState <= STATE_Idle; else CurrentState <= NextState; end … EECS150 Lab Lecture #3

  26. FSMs in Verilog (4) … always @ ( * ) begin NextState = CurrentState; Out = 1’b0; // The case block goes here // Its on the next slide… end endmodule EECS150 Lab Lecture #3

  27. FSMs in Verilog (5) case (CurrentState) STATE_Idle: begin if (In) NextState = STATE_Run; Out = 1’b0; end STATE_Run: begin if (In) NextState = STATE_Idle; Out = 1’b1; end default: begin NextState = STATE_X; Out = 1’bX; end endcase EECS150 Lab Lecture #3

More Related