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Machine Structures Lecture 26 – Virtual Memory I

Machine Structures Lecture 26 – Virtual Memory I. CPU + GPU = “ Fusion ”  AMD recently aquired ATI, maker of high-performance graphics chips, and will create a single, unified processor with BOTH the CPU and GPU on a chip. This could yield cheaper PCs & better performance. +.

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Machine Structures Lecture 26 – Virtual Memory I

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  1. Machine StructuresLecture 26 – Virtual Memory I CPU + GPU = “Fusion”AMD recently aquired ATI, maker of high-performance graphics chips, and will create a single, unified processor with BOTH the CPU and GPU on a chip. This could yield cheaper PCs & better performance + www.sci-tech-today.com/story.xhtml?story_id=13200DIX5QFO

  2. Review: Caches • Cache design choices: • size of cache: speed v. capacity • direct-mapped v. associative • for N-way set assoc: choice of N • block replacement policy • 2nd level cache? • Write through v. write back? • Best choice depends on programs, technology, budget. • Use performance model to pick between choices.

  3. { Thus far { Next: Virtual Memory Another View of the Memory Hierarchy Regs Upper Level Instr. Operands Faster Cache Blocks L2 Cache Blocks Memory Pages Disk Files Larger Tape Lower Level

  4. Memory Hierarchy Requirements • 局部性原理实现了对内存的快速访问（接近Cache的速度），容量不变。这使我们有了推广这一做法的想法： • 为什么不使用下一级存储来提供DRAM内存的速度，而同时具备磁盘的容量呢? • 除了上述想法 • 还能做什么?

  5. Memory Hierarchy Requirements • 允许多个进程同时驻留内存，并受到保护（即不允许一个程序读写另一个的内存） • 地址空间 – 每个程序都似乎拥有自己私有的内存 • 假定代码始于地址0x40000000. 不同的进程代码不同, 都驻留在同一地址. 因此每个程序都对内存有一个自己的视图（view）.

  6. Virtual Memory • Called “Virtual Memory” • Next level in the memory hierarchy: • 给程序的印象是有很大的内存: • 正在运行的 “pages（页面）” 驻留在内存中，其他留在磁盘中. • 同时也允许OS共享内存, 程序互不干扰 • 今天，更重要的是保护，而不是另一层次的内存 • 每个进程（process）认为自己拥有整个内存 • (Historically, it predates caches)

  7. Virtual to Physical Address Translation Program operates in its virtual address space • 每个程序操作其自己的虚拟地址空间; 当然仅仅限于正在运行的程序 • 互不干扰 • OS决定每个程序访问哪个内存 • 硬件提供virtual  physical映射 Physical memory (incl. caches) HW mapping virtual address (inst. fetch load, store) physical address (inst. fetch load, store)

  8. Analogy • 书名好比虚拟内存 • 书的标准索书号好比物理地址 • 目录卡片好比page table, 实现书名到索书号之间的映射 • 卡片上的“当地图书馆”还是“其他分支机构”，正如valid bit表示在主存中还是在磁盘上 • 卡片上, 可在图书馆使用2-小时 (还是借出checkout2周) 正如access rights

  9. Enough space for User D, but discontinuous (“fragmentation problem”) $base+$bound $base Simple Example: Base and Bound Reg ¥ User C User B • Want: • discontinuous mapping • Process size >> mem • Addition not enough!  use Indirection! User A OS 0

  10. Code Static Heap Mapping Virtual Memory to Physical Memory Virtual Memory ¥ • 分为相同大小的块 (约 4 KB - 8 KB) Stack • 虚拟内存的块与物理内存的块间的映射是任意的 (“page”) Physical Memory 64 MB 0 0

  11. Virtual Address Physical Address page 0 0 1K page 0 1K 0 page 1 1K 1024 1K page 1 1024 ... ... ... page 2 1K 2048 ... ... ... page 7 1K 7168 page 31 1K Physical Memory 31744 Virtual Memory Paging Organization (assume 1 KB pages) Page is unit of mapping Addr Trans MAP Page also unit of transfer from disk to physical memory

  12. Page Number Offset Virtual Memory Mapping Function • 无法使用简单函数预测任意映射 • 使用查表法进行映射 • 使用查表法 (“Page Table”) 进行映射: 页号即索引 • 虚拟内存映射函数 • Physical Offset = Virtual Offset • Physical Page Number= PageTable[Virtual Page Number] (P.P.N. also called “Page Frame”)

  13. Virtual Address: page no. offset Page Table ... Page Table Base Reg V A.R. P. P. A. + index into page table Access Rights Physical Page Address Val -id Physical Memory Address . ... Address Mapping: Page Table Page Table located in physical memory

  14. Page Table • page table为操作系统中的一个数据结构，包含虚拟地址到物理位置间的映射 • There are several different ways, all up to the operating system, to keep this data around • 操作系统中运行的每个进程都有自己的page table • 进程的“状态State”包含 PC, all registers, plus page table • OSchanges page tables by changing contents of Page Table Base Register

  15. Requirements revisited Remember the motivation for VM: • 受保护的共享内存 • 不同的物理页可以分配给不同的进程 (共享) • 进程只能访问自己page table中的页面 (protection) • 分离地址空间 • 由于程序工作在虚拟空间中, 不同的程序可以在相同的地址具有不同的数据/代码! What about the memory hierarchy?

  16. ... V A.R. P. P.N. Page Table Access Rights Physical Page Number Val -id P.T.E. V A.R. P. P. N. ... Page Table Entry (PTE) Format • Contains either Physical Page Number or indication not in Main Memory • OS maps to disk if Not Valid (V = 0) • If valid, also check if have permission to use page: Access Rights (A.R.) may be Read Only, Read/Write, Executable

  17. A Page Table B Page Table Paging/Virtual Memory Multiple Processes User A: Virtual Memory User B: Virtual Memory ¥ Physical Memory ¥ Stack Stack 64 MB Heap Heap Static Static 0 Code Code 0 0

  18. Comparing the 2 levels of hierarchy Cache version Virtual Memory vers. Block or Line Page Miss Page Fault Block Size: 32-64B Page Size: 4K-8KB Placement: Fully AssociativeDirect Mapped, N-way Set Associative Replacement: Least Recently UsedLRU or Random (LRU) Write Thru or Back Write Back

  19. Notes on Page Table • 解决碎片问题: 所有块同样大小, 所有的洞都可使用 • OS 必须在磁盘上为每个进程保留 “交换空间Swap Space” • 如果有新的进程, ask Operating System • 若有未使用的页, OS 优先使用他们 • 否则, OS 将内存中一些旧页与磁盘进行交换 • (Least Recently Used to pick pages to swap) • 每个进程有自己的Page Table • 将来会加入一些细节, 但Page Table是虚拟内存的基础

  20. Virtual Memory Problem #1 • 映射每个地址 每个虚拟地址需要通过Page Table访问内存一次一次虚拟内存访问 = 两次物理内存访问 SLOW! • 观察: 由于数据页的局部性, 因此，这些页的虚拟地址变换也必然有局部性 • 因为small is fast, 为什么不使用一个虚拟到物理地址转换的小cache来加速变换呢? • 由于历史的原因, 这个cache被称为 Translation Lookaside Buffer, or TLB

  21. Translation Look-Aside Buffers (TLBs) • TLBs usually small, typically 128 - 256 entries • Like any other cache, the TLB can be direct mapped, set associative, or fully associative hit VA PA TLB Lookup Cache Main Memory Processor miss miss hit data Trans- lation On TLB miss, get page table entry from main memory

  22. Peer Instruction • Locality is important yet different for cache and virtual memory (VM): temporal locality for caches but spatial locality for VM • Cache management is done by hardware (HW), page table management by the operating system (OS), but TLB management is either by HW or OS • VM helps both with security and cost ABC 1: FFF 2: FFT 3: FTF 4: FTT 5: TFF 6: TFT 7: TTF 8: TTT

  23. And in conclusion… • Manage memory to disk? Treat as cache • Included protection as bonus, now critical • Use Page Table of mappings for each uservs. tag/data in cache • TLB is cache of VirtualPhysical addr trans • Virtual Memory allows protected sharing of memory between processes • Spatial Locality means Working Set of Pages is all that must be in memory for process to run fairly well

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