Toward a Methodology for Manufacturability-Driven Design Rule Exploration

Toward a Methodology for Manufacturability-Driven Design Rule Exploration Luigi Capodieci, Puneet Gupta, Andrew B. Kahng, Dennis Sylvester, and Jie Yang Univ. of Michigan, Ann Arbor Univ. of California, San Diego Advanced Micro Devices

Outline • Introduction • Motivation of the restrictive design rule(RDR) approach • RDR embedded design flow • Evaluation metrics • Experimental results • Conclusions and future work

Introduction • Projected gate CD control in sub-wavelength lithography regime (ITRS 2003) • Manufacturable solutions are not known foritalicized numbers • Intel may not use 157nm at 50nm technology node

Introduction (Cont.) • Trends in Mask Cost • Mask data preparation is a serious bottleneck due tothe heavily applied RET • Figure count explodes as dimensions shrink • Data volume for a single mask layer can approach 200GB

Introduction (Cont.) • Trends in Mask Cost (Cont.) • Mask writing time increases from a few days to over a month • Mask set cost increases at an accelerated rate with RET application as the primary driver • ASIC users turn to FPGAs due to high mask cost on low volume designs

Motivation of RDR • RETs need to become part of a cohesive design flow in which libraries and layouts are optimized directly based on conflicts discovered by the RET tool, no longer a post-layout procedure • More conservative design rules or restricted design rules (RDRs) seek to push the manufacturability and performance tradeoff more in favor of the manufacturing side • Apply RDR within ASIC design methodology

RDR Embedded Design Flow

RDR Candidates • Bentgate “on” as baseline (1) • Bentgate line width (5) • Bentgate “off” • Poly to poly spacing (2) • Poly to diffusion spacing (3) • Poly end extension (4) (4) (5) (1) (3) (2)

Value Ranges of RDR • Use IBM 0.13μm technology as “default” • Guideline • Start from the most “free” design rule set, i.e., for best performance in delay & area – “bentgate on” as baseline • Create more conservative design rules • Only one rule differs from “Default” rule set • Moving to more conservative direction,e.g. increasing poly to poly spacing, line width, etc. • The parentheses contain the corresponding labels in all figures

EPE<0 EPE>0 Value Ranges of RDR (Cont.) • We use edge placement errors (EPEs) as a quantifying metric to determine value range • Measure how closely a printed feature actually reflects the corresponding designed feature • Defined as the distance between the edges of printed image and drawn feature (positive value indicates printed image outside of drawn feature boundary while negative value indicates it’s inside) EPE<0 EPE<0 EPE>0 EPE>0 (a) (b)

Value Ranges of RDR (Cont.) • Determine the “forbidden pitch” • Define 0.42μm to 0.72μm as the forbidden pitch rangeaccording to simulation results

OPC Fracture Mask Evaluation Metrics • For manufacturability: EPE and average CD • EPEs to measure the effectiveness of OPC • Goal is to achieve a tight EPE distribution with mean around zero • Using average CD to compensate for the limitation of EPE • The EPE distributions can not correctly reflect CD • Use average gate-length calculated from a printed non-uniform gate area for further evaluation • For OPC cost: MEBES data volume • MEBES is the standard mask writer format • The explosion of MEBES data volume due to RETs has made mask data preparation a serious bottleneck. • It shows the complexity of OPC layer and reflects the mask cost

Outline • Introduction • Motivation of the restrictive design rule (RDR) approach • RDR embedded design flow • Evaluation metrics • Experimental results • Conclusions and future work

Experimental Results • Impact of defocus on maximum EPE levels vs. RDRs

Experimental Results • Impact of defocus on CD distribution (circuit: c7552)

Experimental Results • Impact of defocus on functional yield for a fixed 10% Lgate variation (circuit: c7552)

Experimental Results • Scattering bars (or sub-resolution assist features) (circuit: c7552)

Experimental Results • Approach of the single pitch RDR (circuit: c7552) • Single pitch, single orientation • Poly pitch larger than default value to allow contact be inserted • Pseudo single pitch (97.6% fixed at a single value) • AOI, OAI cells are excluded • With SRAFs tuned for the single pitch library at 0.1µm defocus

Experimental Results • Circuit performance analysis

Experimental Results • Tradeoff between functional yield at 10% EPE tolerance and mask cost with loose OPC for corner correction (circuit: c7552)

Conclusions and Future Work • Restrictive design rules can result in more robust and cost-effective circuits without sacrificing performance • Data volume reduction on the order of 20-30% relative to baseline rule set • Worst-case EPE reduction nearly 50% with small penalty on performance • RDR sets can be formulated to support sub-wavelength lithography by providing substantial cost reductions with negligible performance tradeoff

Conclusions and Future Work • Multi-layer design rules • Metal design rules • Besides poly, OPC is also heavily applied on metal.Metal design rules are promising candidates for RDRs • Contact design rules • A great number of correcting features are inserted to maintain the fidelity of the layer covering the contact while the goal should be obtain enough overlap area • E.g., avoid contact very close to metal line end mayreduce both the OPC cost on metal and the possibilityfor an open fault • Performance analysis for post-OPC • Reduce correction cost on field poly whenever possible

Toward a Methodology for Manufacturability-Driven Design Rule Exploration