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Project mid presentation

Symbol Generator. Project mid presentation. Presented by : Olga Liberman & Yoav Shvartz Supervisor : Moshe Porian 1 semester project 29.1.2012. Contents. Reminder Top Architecture Micro architecture Schedule. Intro.

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Project mid presentation

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  1. Symbol Generator Project mid presentation • Presented by : Olga Liberman & YoavShvartz • Supervisor : Moshe Porian • 1 semester project • 29.1.2012

  2. Contents • Reminder • Top Architecture • Micro architecture • Schedule

  3. Intro • Generating symbols on display screens is an essential operation these days. • Commonly used in varies applications: Military applications Televisions Mobile phones

  4. Reminder - Specifications • Generating symbols on display screen using: • Cyclone II FPGA • Host communication via UART protocol • Internal communication via Wishbone protocol • Input - Grayscale symbols 32 x 32 pixels • saved in external SDRAM • Output - Grayscale image resolution 640x480 pixels • Main clock freq. 133MHz • VESA (monitor) freq. 40 Hz

  5. Top Architecture UART TX Path RX Path UART WBS WBM WBM Host (Matlab) opcode Wishbone INTERCON WBS Memory Management WBS WBM VGA Display WBS Display Controller WBM IS42S16400 SDRAM WBS SDRAM Controller VESA

  6. Reminder - Interaction SDRAM 2^12 X 2^8 FIFO A/B 1 Symbol #1 1 RAM 13X300 bit Symbol #2 Op-Code 0/1 • Address of the symbol in the SDRAM X Y Address of symbol (0,0) in the SDRAM 1 Address of symbol (0,1) in the SDRAM Symbol #N 1 1 Address of symbol (14,19) in the SDRAM 1 1 1 1 1 8X640 bit SCREEN 640X480 31 31 31 31 31 32 32 32 32 32

  7. SDRAM 2 2 2 2 2 FIFO A 2 2 2 2 2 FIFO B 1 SCREEN 1 1 1 1 1 1 1 1 31 31 31 31 31 32 32 1 1 32 32 32 1 1 1 1

  8. Top Architecture UART TX Path RX Path UART WBS WBM WBM Host (Matlab) Wishbone INTERCON WBS Memory Management WBS WBM VGA Display WBS Display Controller WBM IS42S16400 SDRAM WBS SDRAM Controller VESA

  9. Micro Architecture WBS Opcode WBS bus Opcode Unite OPU VESA Bus Data bus - 133 MHz 40 Hz Write bus Vsync RAM Opcode Store Re Mng Valid Data Read bus Memory Reg FIFO A Write bus Data Re-Mng Data A MUX Rd _en A/B WBM Data B SDRAM WBM bus FIFO B VESA Controller Write bus MUX Sel Dual Clk FIFO Req_in_trg

  10. IDLE reset Wbs_cyc = '1' Wbs_stb = '1' MP3 state Opcode_i(23:16) <= wbs_data_i(7:0) Counter++ Opu_data_out <= opcode_i MP1 state Opcode_i(23:16) <= wbs_data_i(7:0) Counter++ Wbs_cyc = '1' Wbs_stb = '1' Counter < wbs_tga_i MP2 state Opcode_i(15:8) <= wbs_data_i(7:0) Counter++ Wbs_cyc = '1' Wbs_stb = '1' Wbs_cyc = '1' Wbs_stb = '1' • Micro Architecture - OPU Goal: 1.Unites every 3 packs of MPD into 1 opcode by a FSM. 2.Sending the changes to Opcode Store • opcode • MPD 1 • MPD 2 • MPD 3 MPD = Message Pack Data

  11. Micro Architecture – OPUpins: Clk_133 Opu_wr_en reset Opu_data_out[23..0] Wbs_adr_i [9..0] Opu_cnt[9..0] Wbs_tga_i [9..0] Opcode Unite Wbs_dat_i [7..0] Wbs_ack_o Wbs_cyc_i Wbs_stall_o Wbs_stb_i Wbs_err_o

  12. Micro Architecture WBS Opcode WBS bus Opcode Unite OPU VESA Bus Data bus - 133 MHz 40 Hz Write bus Vsync RAM Opcode Store Re Mng Valid Data Read bus Memory Reg FIFO A Write bus Data Re-Mng Data A MUX Rd _en A/B WBM Data B SDRAM WBM bus FIFO B VESA Controller Write bus MUX Sel Dual Clk FIFO Req_in_trg

  13. Micro Architecture – Opcode Store Goal: Stores commands from the OPU. Sending the changes to RAM. 0/1 • Com add X Y Size : 300 x 24 (rows x bits) RAM_adr_wr[8..0] = 20*x + y • Com_type = ‘0’ (remove a symbol) RAM_data_in[12..0]= "0…0" • Com_type = ‘1’(add a symbol)  RAM_data_in[12..0]= "com_add".

  14. Micro Architecture – Opcode Storepins: RAM_adr_wr[8..0] Clk_133 RAM_wr_en reset RAM_data_in[12..0] rd_mng_en Opcode Store 24x 300 (bit x row) Opu_cnt[9..0] Op_str_ready Op_str_valid Op_str_empty Op_str_data_in[23..0] Op_str_full Op_str_used[8..0] Op_str_rd_start

  15. Micro Architecture WBS Opcode WBS bus Opcode Unite OPU VESA Bus Data bus - 133 MHz 40 Hz Write bus Vsync RAM Opcode Store Re Mng Valid Data Read bus Memory Reg FIFO A Write bus Data Re-Mng Data A MUX Rd _en A/B WBM Data B SDRAM WBM bus FIFO B VESA Controller Write bus MUX Sel Dual Clk FIFO Req_in_trg

  16. Micro Architecture - RAM 20 Goal: Stores the address of the symbol in the SDRAM. Size: 13X300 bits Video Frame Address of symbol (0,0) in the SDRAM RAM 15 SDRAM Address of symbol (14,19) in the SDRAM Address of symbol (0,1) in the SDRAM

  17. Micro Architecture – RAMpins: Clk_133 reset RAM_adr_wr[8..0] RAM 13 x 300 (bit x row) RAM_data_out[12..0] RAM_wr_en RAM_out_valid RAM_data_in[12..0] RAM_adr_rd[8..0] RAM_rd_en

  18. Micro Architecture WBS Opcode WBS bus Opcode Unite OPU VESA Bus Data bus - 133 MHz 40 Hz Write bus Vsync RAM Opcode Store Re Mng Valid Data Read bus Memory Reg FIFO A Write bus Data Re-Mng Data A MUX Rd _en A/B WBM Data B SDRAM WBM bus FIFO B VESA Controller Write bus MUX Sel Dual Clk FIFO Req_in_trg

  19. Micro Architecture – Rd_Mng Goal: • The "brain" of the Symbol Generator block Functionality: • Calculating relevant row in the RAM and receiving data. • Calculating row and column in the SDRAM (where the symbol sits). • Managing the toggling between the two FIFOs, using FSM.

  20. Micro Architecture – Rd_Mng FSM: reset IDLE RAM updated Rd_mng_en Finished deliver last row to DC FIFO WRITE A READ B (req_in_trg) AND (last row of the frame) Req_in_trg WRITE A READ B READ A WRITE B req_in_trg (req_in_trg) AND (NOT last row of the frame)

  21. RAM_rd_en Clk_133 RAM_adr_rd[8..0] Micro Architecture – Rd_Mngpins: reset Wbm_add_o[9..0] RAM_data_out[12..0] Wbm_dat_o[7..0] Wbm_tga_o[9..0] RAM_out_valid Wbm_cyc_o Read_Manager (=RM) Wbm_std_o Wbm_dat_i[7..0] To Memory Management FIFO_A_rd_en Wbm_stall_i From Memory Management FIFO_A_wr_en Wbm_ack_i FIFO_A_data_in[7..0] Wbm_err_i FIFO_B_rd_en FIFO_B_wr_en req_in_trg FIFO_B_data_in[7..0]

  22. Micro Architecture WBS Opcode WBS bus Opcode Unite OPU VESA Bus Data bus - 133 MHz 40 Hz Write bus Vsync RAM Opcode Store Re Mng Valid Data Read bus Memory Reg FIFO A Write bus Data Re-Mng MUX Data A Rd _en A/B WBM Data B SDRAM WBM bus FIFO B VESA Controller Write bus MUX Sel Dual Clk FIFO Req_in_trg

  23. Micro Architecture – FIFO A/B Goal: • The toggle FIFOs • Size: 8x640 bits • Pins: Clk_133 reset FIFO 8x640 (bit x row) FIFO_data_out[7..0] FIFO_data_in[7..0] FIFO_out_valid FIFO_wr_en FIFO_rd_en

  24. Micro Architecture WBS Opcode WBS bus Opcode Unite OPU VESA Bus Data bus - 133 MHz 40 Hz Write bus Vsync RAM Opcode Store Re Mng Valid Data Read bus Memory Reg FIFO A Write bus Data Re-Mng Data A MUX Rd _en A/B WBM Data B SDRAM WBM bus FIFO B VESA Controller Write bus MUX Sel Dual Clk FIFO Req_in_trg

  25. Micro Architecture – D.C FIFO Goal: • Transferring data from FIFOs (133MHz) to VESA (40Hz) • Pins: arst Q [7..0] Data [7..0] rdempty rdclk D.C FIFO rdreq wrfull wrclk Wrusedw[12..0] wrreq

  26. Schedule

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