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Midterm Presentation

Midterm Presentation. Project Name: Serial Communication Analyzer Company Name: Digital laboratory Presenter Name: Igal Kogan Alexander Rekhelis Instructor: Hen Broodney Semester:Winter 2001/2. Project Goals.

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Midterm Presentation

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  1. Midterm Presentation Project Name: Serial Communication Analyzer Company Name: Digital laboratory Presenter Name: Igal Kogan Alexander Rekhelis Instructor: Hen Broodney Semester:Winter 2001/2

  2. Project Goals • Implementation of testing and debugging device for serial communication protocol RS-232 and DSP protocol McBSP. • Both protocols are encoded and/or decoded by Altera FPGA. Also PCI Interface protocol, that implemented in PCI MegaCore, is managed by Altera FPGA. • The design will base on Altera Flex PCI Development Kit and the external devices will connect through bridges that are specially designed as RS-232 and McBSP protocols buffers.

  3. Abstract The device will manage the data in several ways: 1) As data buffer it will transfer the data from the input device to the output device. 2) As communication analyzer it will read the data from input, send it to PC through PCI Bus for processing, and according to user commands will send the updated data to output. Note: Since the communication is bi-directional, input and output devices can be switched constantly.

  4. Highlights of RS232 protocol • RS-232 is an electrical interface standard between Data Terminal Equipment (DTE) and Data Circuit-Terminating Equipment (DCE) such as modems, PALM, mouse and so. • RS-232 is used for asynchronous data transfer as well as synchronous links. • It appears under different incarnations such as RS-232C, RS-232D, V.24, V.28 or V.10 but essentially all these interfaces are interoperable.

  5. Highlights of McBSP protocol • Full-duplex communication • Double-buffered data registers, which allow a continuous data stream • Independent framing and clocking for receive and transmit • Direct interface to industry-standard analog interface chips (AICs), and other serially connected analog-to-digital (A/D) and digital-to-analog (D/A) devices • External shift clock or an internal, programmable frequency shift clock for data transfer • Autobuffering capability through the 5-channel DMA controller.

  6. Abstract (cont.) RS-232 RS-232 Serial Communication Analyzer McBSP McBSP

  7. System Block Diagram RS-232 Communication Device RS-232 Communication Device Altera Flex PCI Development Kit McBSP Communication Device McBSP Communication Device PCI WinDriver GUI

  8. Altera PCI Development Board

  9. Hardware • All hardware will be implemented on Altera FLEX PCI Development Kit. • One channel for RS-232 communication is already placed on the kit. The implementation of the second RS-232 communication channel that connects to the Altera on the kit and also the implementation of the connections between two McBSP channels on DSP board to the Altera on the kit board are currently in progress. • We already purchased all needed elements and we will finish the rest of the pin connections shortly.

  10. RS-232 pin out (addition)

  11. PC Com Port - EIA-574 RS-232 pin out DB-9 pin used for Asynchronous Data

  12. McBSP pin out (addition)

  13. McBSP Interface Signals Pin I/O/Z† Description CLKR I/O/Z Receive clock CLKX I/O/Z Transmit clock CLKS I External clock DR I Received serial data DX O/Z Transmitted serial data FSR I/O/Z Receive frame synchronization FSX I/O/Z Transmit frame synchronization

  14. Software • We are currently focused on RS232 protocol implementation. The communication can be handled at: 1200, 2400, 4800, 9600, 19200 baud rate. In the future the rates can be increased if needed. The communication rate and condition (with or without handshake) will be determined by the GUI through the WinDriver. • Control Logic block will provide the proper interactions between PCI Core and RS232 or McBSP communication blocks (by local bus).

  15. System modules diagram (FPGA) RS-232 Protocol Control Logic RS-232 Protocol McBSP Protocol McBSP Protocol PCI MegaCore

  16. PCI Core PCI Bus Local Bus חלוקת ה-PCI Core ליחידות לוגיות, כפי שמומש ע”י חברת Altera. תפקידו למנשק בין ה-PCI Bus לבין Control Logic Block.

  17. FPGA block diagram

  18. Schedule • Schedule milestones are: Phase 1 Phase 2 Phase 3 Oct Nov Dec Jan Feb Mar Apr May Jun Jul Phase1 – Hardware Design Phase2 – Software Design Phase3 – Debug

  19. Schedule (cont.) • לוח זמנים: • 12/2001 – 01/2002 : הרכבת הפרוייקט , בדיקת התכנון – RS-232 • 23/12/2001 - הצגת דו"ח אמצע לצוות מעבדה. • 30/12/2001 - הרכבת החומרה. • 01/01/2002 - יציאה למילואים של אחד מאנשי הצוות. • 14/01/2002 - סיום מימוש פרוטוקול RS-232 . • 21/01/2002 - בדיקות עבודת הפרוטוקול RS-232 . • 30/01/2002 - בדיקות עבודת הפרוטוקול RS-232 + איתור תקלות. • 04/02/2002 - הכנות לבחינות סוף סמסטר. • 02/2002 – 03/2002 : בחינות סוף סמסטר. • 03/2002 : הצגת חלק א' - הצגת כרטיס כולל בדיקות ראשוניות, עבודה בפרוטוקול RS-232 .

  20. Serial Communication Analyzer תודה רבה

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