Low power circuits for a 2 5 v 10 7 to 86 gb s serial transmitter in 130 nm sige bicmos
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Low-Power Circuits for a 2.5-V, 10.7-to-86-Gb/s Serial Transmitter in 130-nm SiGe BiCMOS PowerPoint PPT Presentation


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Timothy O. Dickson and Sorin P. Voinigescu Edward S. Rogers, Sr. Dept of Electrical and Computer Engineering University of Toronto CSICS November 15, 2006. Low-Power Circuits for a 2.5-V, 10.7-to-86-Gb/s Serial Transmitter in 130-nm SiGe BiCMOS. Outline. Motivation

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Low-Power Circuits for a 2.5-V, 10.7-to-86-Gb/s Serial Transmitter in 130-nm SiGe BiCMOS

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Timothy O. Dickson and Sorin P. Voinigescu

Edward S. Rogers, Sr. Dept of Electrical and Computer Engineering

University of Toronto

CSICS

November 15, 2006

Low-Power Circuits for a 2.5-V, 10.7-to-86-Gb/s Serial Transmitter in 130-nm SiGe BiCMOS


Outline

  • Motivation

  • High-speed, low-power design techniques

  • 2.5-V, 80-Gb/s BiCMOS Transmitter

  • Measurement results

  • Conclusions


1 x 100-Gb/s

Next Generation High-Speed Wireline: 100-Gb/s Ethernet

New design challenges as fundamental

frequencies enter mm-wave regime


Power Consumption

should consume less

power than

100 Gb/s

10 x 10 Gb/s

State-of-the-art High-Speed Transceivers


Power Consumption

should consume less

power than

100-Gb/s 4:1 MUX?


MOSFETs vs HBTs

  • HBT @ peak-fT VBE = 900mV… and does not scale!

  • 130-nm nMOS @ peak-fT VGS = 750mV… and decreasing!


BiCMOS logic family reduces supply voltage

Reduce tail current with inductive peaking

CLDV2

LP =

3.1 IT2

10 mm

Stacked inductors

Power reduction techniques

43-GHz latch consumes only 20mW


40-GHz PLL

Output Driver

On-chip

PRBS for

BIST

8:1 MUX

Transmitter Block Diagram


SF for voltage headroom

EF for higher bandwidth

2.5-V, 87-Gb/s BiCMOS Selector

86-Gb/s selector consumes 60mW


2.5-V, 80-Gb/s BiCMOS Pre-Emphasis Driver

MOS gm and input capacitance relatively constant as bias current changes.

Excellent for output stages with adjustable amplitude control.


2.5-V, 80-Gb/s BiCMOS Pre-Emphasis Driver

130-nm MOSFETs

switching at 80-Gb/s!


2.5-V, 80-Gb/s BiCMOS Pre-Emphasis Driver

Adjustable pre-emphasis for operation up to 80-Gb/s

Boosts high-frequency content to compensate for line losses.

Output match S22 < -10dB up to 94 GHz.


36-43 GHz Colpitts VCO

  • SiGe HBTs used as negative resistance generators.

  • Differential tuning to reject common-mode noise.

  • Maximize tank swing, bias HBTs at NFMIN for low phase noise

-105 dBc/Hz @ 1-MHz offset


Die Photograph

PLL

1.5 mm

PRBS

+ 8:4 MUX

4:1 MUX +

Output Driver

1.8 mm


Measured Results: 80-Gb/s

Running for more than 1 hour continuously in the lab.

Jitter: 560 fs (rms) , Rise/fall time: 4-5 ps, Amplitude: 300 mV


Verification of Correct Multiplexing

Using pattern capture capabilities of

the Agilent 86100C DCA


Verification of Correct Multiplexing

Examine the tone spacing using

Agilent E4448A PSA


80-Gb/s: Amplitude Control

Little degradation in eye quality as amplitude

varies from 100mV to 300 mV per side


Maximum Data Rate: 87-Gb/s

685 MHz

87 GHz

= 685 MHz

127


Maximum Data Rate vs. Temp.

92-Gb/s @ 0oC

71-Gb/s @ 100oC


Comparison


Conclusions

  • Described methods for power reduction in high-speed building blocks.

    • Use BiCMOS topology to lower supply voltage.

    • Trade off bias current for inductive peaking.

  • Applied these principles to the design of the first 87-Gb/s serial transmitter, which consumes less power than any 40-Gb/s TX reported to date.

  • As compared with state-of-the-art CMOS, this work shows that you can achieve double the data rate with half the power dissipation simply by adding the SiGe HBT option.


Acknowledgements

  • STMicroelectronics Crolles for chip fabrication

  • STMicroelectronics, Gennum, CITO, and NSERC for financial support

  • CMC for CAD tools

  • CFI and OIT for equipment and test support


Questions?


Backups


VGS

VBE

VBE

VDS = 0V!

VGS

DC Considerations

Need CM resistor in

43-GHz clock buffer


Future Directions: Futher Power Savings

Reduce supply voltage to 1.8V by removing current sources.

38% power savings would result in 86-Gb/s TX that consumes 825 mW.


SiGe Building Block Supply Voltage

DC drops dictate at least 3.3-V supply voltage

150 mV IR

900 mV VBE

900 mV VBE

750 mV VCE

600 mV VCE + IR

Unlike CMOS, supply voltage does not scale!!


CMOS vs. SiGe BiCMOS

SiGe HBT has 2-generation speed advantage


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