ABCD: “ Booleanizing ” Analog Systems for Verifying Chips. Aadithya V. Karthik , Sayak Ray, Pierluigi Nuzzo , Alan Mishchenko , Robert Brayton , and Jaijeet Roychowdhury EECS Dept., The University of California, Berkeley. Feb 2014, BEARS, Berkeley. The Problem: Verifying a Chip.
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Aadithya V. Karthik,
Sayak Ray, PierluigiNuzzo, Alan Mishchenko,
Robert Brayton, and JaijeetRoychowdhury
EECS Dept., The University of California, Berkeley
Feb 2014, BEARS, Berkeley
Want to verify complete system
e.g., eye opening height > 1V?
Proof or counter-example needed
Best verification tools = all Boolean, no continuous
Verification tools accept
Formal verification, high-speed simulation, test pattern generation, ...
… for the full combined system!
Example: Channel + Equalizer
I/O signaling system