Abcd booleanizing analog systems for verifying chips
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ABCD: “ Booleanizing ” Analog Systems for Verifying Chips. Aadithya V. Karthik , Sayak Ray, Pierluigi Nuzzo , Alan Mishchenko , Robert Brayton , and Jaijeet Roychowdhury EECS Dept., The University of California, Berkeley. Feb 2014, BEARS, Berkeley. The Problem: Verifying a Chip.

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ABCD: “ Booleanizing ” Analog Systems for Verifying Chips

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Abcd booleanizing analog systems for verifying chips

ABCD: “Booleanizing” AnalogSystems for Verifying Chips

Aadithya V. Karthik,

Sayak Ray, PierluigiNuzzo, Alan Mishchenko,

Robert Brayton, and JaijeetRoychowdhury

EECS Dept., The University of California, Berkeley

Feb 2014, BEARS, Berkeley


The problem verifying a chip

The Problem: Verifying a Chip

Specification

Chip designers

Chip


The problem ams verification

The Problem: AMS Verification

Want to verify complete system

e.g., eye opening height > 1V?

Proof or counter-example needed

Example: SERDES

PLL

Analog

parts

CDR

I/O

Surrounded by

Digital Logic

>1V


Our approach booleanize the analog parts

Our approach: “Booleanize” the analog parts

Analog models

Challenge:

Digital models

(don't mix)

+

ABCD: Boolean

approximation

ALL

BOOLEAN

Continuous

Boolean

Best verification tools = all Boolean, no continuous

SAR-ADC

Boolean T/H

approximation

Boolean

comparator

approximation

Boolean DAC

approximation

Analog components

Digital components

Verification tools accept

Fast

Formal verification, high-speed simulation, test pattern generation, ...

… for the full combined system!


Abcd in action

ABCD in action

ABCD

Purely Boolean

Model

Analog Circuit

Example: Channel + Equalizer

Bit Sequence


Circuits successfully booleanized

Circuits Successfully Booleanized

Delay line

Charge pump

Power grid

Equalizer

I/O signaling system

SAR-ADC


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