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ENG2410 Digital Design: Week #4 “Combinational Logic Design”

ENG2410 Digital Design: Week #4 “Combinational Logic Design”. S. Areibi School of Engineering University of Guelph. Resources. Chapter #4, Mano Sections 4.1 Combinational Circuits 4.3 Decoding 4.4 Encoding 4.5 Multiplexers 4.6 Comb Function Implementations. Week #4: Topics. Decoders

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ENG2410 Digital Design: Week #4 “Combinational Logic Design”

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  1. ENG2410Digital Design: Week #4“Combinational Logic Design” S. Areibi School of Engineering University of Guelph

  2. Resources Chapter #4, Mano Sections • 4.1 Combinational Circuits • 4.3 Decoding • 4.4 Encoding • 4.5 Multiplexers • 4.6 Comb Function Implementations

  3. Week #4: Topics • Decoders • Combinational circuit Implementation • Encoders • Priority Encoders • Multiplexers • Combinational Circuit Implementation • Demultiplexers

  4. Decoders and Multiplexors Decoders and Multiplexors are important and fundamental circuits that are found in any Central Processing Unit (CPU).

  5. Decoders

  6. Devices on a Bus • I have 4 devices to put info on a Bus • I must have only one device active at a time! • I will need 4 wires from my Control Unit • If I need to communicate with more devices then I will need many wires!! Control Unit Enable Device #0 Disable Device #1 Disable Device #2 Disable Device #3 BUS

  7. Address Decoding • I have 4 devices to put info on a Bus • I must have only one device active at a time! • But! I can afford to have only 2 wires from my control unit Control Unit Device #0 0 1 Device #1 1 0 1 0 0 0 0 0 0 0 Device #2 Device #3 BUS

  8. Decoders • Are circuits with n inputs and 2n outputs • Drives high the output corresponding to binary code of input • Several Applications: Address Decoding, … D0 A D1

  9. 2-to-4 Line Decoder Notice they are minterms

  10. Other Decoders Examples: • 3-to-8 Decoder • 4-to-16 Decoder • Binary to Hex, e.t.c • Binary to Octal, 3-to-8 Line Decoder 4-to-16 Line Decoder 8 3 4 16

  11. Truth Table, 3-to-8 Decoder • Example: Binary to Octal, Binary to Hex, e.t.c Notice they are minterms • Binary to Octal, A0 3-to-8 Line Decoder A1 A2

  12. 3-to-8 Line Decoder Schematic

  13. 2-to-4 with Enable Why use an Enable?

  14. Enable Used for Expansion A2 A1 A0 0 0 0 0 1 0 1 0 0 1 1 0 0 1 0 0 1 1 1 1 0 1 1 1 1 0 0 1 1 0

  15. Usage for Decoders • Binary to Octal/Hex converters. • Selecting memory banks, for example 4 memory banks can be selected individually using 2 address lines. • Implementing logic circuits! • Decoders are used in Micro Computer Interfacing for Keyboard and Display applications.

  16. Address Decoding CPU Memory Bank #1 Memory Bank #2 Memory Bank #3 Memory Bank #4

  17. Decoders: Logic Implementation

  18. Decoders as General-purpose Logic n:2n decoder implements any function of n variables • With the variables used as control inputs • Enable inputs tied to 1 and • Appropriate minterms summed to form the function Decoder generates appropriate minterm based on control signals (it "decodes" control signals)

  19. Decoders as General-purpose Logic Example: Implement the following Boolean functions • S(A2,A1,A0) = SUM(m(1,2,4,7)) • C(A2,A1,A0) = SUM(m(3,5,6,7)) • Since there are three inputs, we need a 3-to-8 line decoder. • The decoder generates the eight minterms for inputs A0,A1,A2 • An OR GATE forms the logical sum minterms required.

  20. Decoders as General-purpose Logic S(A2,A1,A0) = SUM(m(1,2,4,7)) S

  21. Decoders as General-purpose Logic C(A2,A1,A0) = SUM(m(3,5,6,7)) C

  22. 0 A'B'C'D'1 A'B'C'D2 A'B'CD'3 A'B'CD4 A'BC'D'5 A'BC'D6 A'BCD'7 A'BCD8 AB'C'D'9 AB'C'D10 AB'CD'11 AB'CD12 ABC'D'13 ABC'D14 ABCD'15 ABCD0 A'B'C'D'1 A'B'C'D2 A'B'CD'3 A'B'CD4 A'BC'D'5 A'BC'D6 A'BCD'7 A'BCD8 AB'C'D'9 AB'C'D10 AB'CD'11 AB'CD12 ABC'D'13 ABC'D14 ABCD'15 ABCD F1 4:16DEC Enable A B C D Example • F1 = A' B C' D + A' B' C D + A B C D

  23. Encoders

  24. Encoder • Encoder is the opposite of decoder • 2n inputs (or less – maybe BCD in) • n outputs • Examples: • Octal to binary conversion • Hexadecimal to binary conversion

  25. Octal to Binary Encoder

  26. Design of Encoder A0 = D1 + D3 + D5 + D7

  27. Multiplexors

  28. Multiplexer (or Mux) • Selects one of a set of inputs to pass on to output • For Every 2n inputs we need n select lines • Applications: Useful for choosing from sets of data • Memory or register to ALU In0 Out In1 MUX In2 In3 S1 S0

  29. 2-Input Multiplexer

  30. 4-to-1 Line Multiplexer

  31. Quad 2-to-4 Line Mux • Select one set of 4 lines

  32. Muliplexors: Logic Implementation

  33. Implementing Logic • 2n:1 multiplexer implements any function of n variables • With the variables used as control inputs and • Data inputs tied to 0 or 1 • In essence, a lookup table • Example: F(A,B) = m0 + m2 = A'B' + AB’

  34. Muxes as General-purpose Logic • 2n:1 multiplexer implements any function of n variables • With the variables used as control inputs and • Data inputs tied to 0 or 1 • In essence, a lookup table • Example: F(A,B,C) = m0 + m2 + m6 + m7 = A'B'C' + A'BC' + ABC' + ABC 10100011 01234567 F 8:1 MUX S2 S1 S0 A B C

  35. 10100011 01234567 A B C F0 0 0 10 0 1 00 1 0 10 1 1 01 0 0 01 0 1 01 1 0 11 1 1 1 8:1 MUX S2 S1 S0 A B C Muxes as General-purpose Logic • 2n-1:1 mux can implement any function of n variables • With n-1 variables used as control inputs and • Data inputs tied to the last variable or its complement • Example: • F(A,B,C) = m0 + m2 + m6 + m7 = A'B'C' + A'BC' + ABC' + ABC Not Optimized How to use a 4:1 MUX Instead? • Use inputs A, B as the selection lines for the 4:1 MUX since we will only have two selection lines • Find a relationship between C (the third input) and F F

  36. 10100011 01234567 A B C F0 0 0 10 0 1 00 1 0 10 1 1 01 0 0 01 0 1 01 1 0 11 1 1 1 C'C'01 C'C'01 0123 F 4:1 MUX 8:1 MUX S1 S0 A B S2 S1 S0 A B C Muxes as General-purpose Logic • 2n-1:1 mux can implement any function of n variables • With n-1 variables used as control inputs and • Data inputs tied to the last variable or its complement • Example: • F(A,B,C) = m0 + m2 + m6 + m7 = A'B'C' + A'BC' + ABC' + ABC Not Optimized Optimized How to use a 4:1 MUX Instead? F

  37. Demuliplexors

  38. Demultiplexer Takes one input out to one of 2n possible outputs

  39. VHDL Implementations

  40. Decoder: (VHDL  Data Flow) Example: 2-to-4 decoder D3 entity dec_2_to_4 is port ( A0, A1: in std_logic; D0, D1, D2, D3: out std_logic); end entity dec_2_to_4; A(1) D2 Interface A(0) D1 D0 architecture dataflow1 of dec_2_to_4 is Signal A0_n, A1_n: std_logic; begin A0_n <= not A0; A1_n <= not A1; D0 <= A0_n and A1_n; D1 <= A0 and A1_n; D2 <= A0_n and A1; D3 <= A0 and A1; end architecture dataflow1; A1_n A0_n Functionality

  41. When Else Statement mux: Y <= D0when S1 = ‘0’ and S0 = ‘0’ else D1when S1 = ‘0’ and S0 = ‘1’ else D2when S1 = ‘1’ and S0 = ‘0’ else D3;

  42. VHDL of 4-to-1 Multiplexer using When/Else -- 4-to-1 Line Mux; Conditional Dataflow VHDL Descrip library ieee; use ieee.std_logic_1164.all entity multiplexer_4_to_1 is port (S: in std_logic_vector(1 downto 0); D: in std_logic_vector(3 downto 0); Y: out std_logic; end multiplexer_4_to_1;

  43. Cont .. Dataflow VHDL Description architecture function_table of multiplexer_4_to_1 is -- Using When Else Begin Y <= D(0) when S = “00” else D(1) when S = “01” else D(2) when S = “10” else D(3) when S = “11” else `X’; end function_table;

  44. Decoder: Data Flow #2 Example: 2-to-4 decoder D(3) entity dec_2_to_4 is port ( A : in std_logic_vector(1 downto 0); D : out std_logic_vector(3 downto 0) ); end entity dec_2_to_4; architecture dataflow2 of dec_2_to_4 is begin D <= "0001" when A = "00" else "0010" when A = "01" else "0100" when A = "10" else "1000" when A = "11" else "XXXX"; end architecture dataflow2; A(1) D(2) Interface A(0) D(1) D(0) Functionality

  45. dataflow VHDL Design Styles VHDL Design Styles behavioral (algorithmic) structural Components and interconnects Concurrent statements Sequential statements • Registers • State machines • Test benches Subset most suitable for synthesis

  46. Structural VHDL Description of 2-to-4 Line Decoder

  47. Structural VHDL Description“Entity Declaration” -- 2-to-4 Line Decoder; structural VHDL Description library ieee; use ieee.std_logic_1164.all entity decoder_2_4_w_enable is port (EN, A0, A1 : in std_logic; D0, D1, D2, D3 : out std_logic); end decoder_2_to_4_w_enable;

  48. Structural VHDL Description (Signals) A1_n A0_n N0 N1 N2 N3

  49. Structural VHDL Description (Components) architecture structural1_1 of decoder_2_to_4_w_enable is component NOT1 port(in1: in std_logic; out1: out std_logic); end component; component AND2 port(in1, in2: in std_logic; out1: out std_logic); end component;

  50. Structural VHDL Description(Connecting components) A1_n A0_n architecture structural1_1 of decoder_2_to_4_w_enable is -- component NOT1 declaration -- component NAND2 declaration signal A0_n, A1_n, N0, N1, N2, N3: std_logic; begin g0: NOT1 port map (in1 => A0, out1 => A0_n); g1: NOT1 port map (in1 => A1, out1 => A1_n); …… …… …… end structural_1; component NOT1 port(in1: instd_logic; out1: outstd_logic); end component;

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