Yet Another Kind of Self-Reparable Logics for Raising Manufacturing Yield

1. Yet Another Kind of Self-Reparable Logics for Raising Manufacturing Yield Date: 2012/5/25 Speaker: Ching-Yi Huang

2. Outline • Introduction • Preliminaries & Related Works • Logic Redundancy and Fault Tolerance • Optimization on Fault Masking Rate • Experimental Results • Conclusion

3. Introduction • Technology scales down • Correctness rate < 100% • Soft error • Hard error

4. Introduction • Fault tolerance • Triple modular redundancy (TMR) • NUTMR • … • Disadvantage • High area overhead (as high as 226%)

5. Introduction • Logic Masking • Render fault unobservable by preventing them from being activated or sensitized • Mitigate soft errors [4] by adding some redundant wires to the circuit • [4] S. Almukhaizim and Y. Makris. Soft error mitigation through selective addition of functionally redundant wires. Reliability, IEEE Transactions on, 57(1):23 –31, march 2008.

6. Introduction • Advantages of redundant wire addition (rewiring) • Can be applied to the hard error domain • Has less area overhead than TMR • Alternative and target wire can be well selected to avoid affecting timing critical paths • Rewiring can work seamlessly with higher-level fault tolerant design

7. Introduction • Features • Only add gates and wires without removing existing circuit components – mutual redundancy • Analyze the effect of redundant wire addition • Enhance the manufacturing yield - proof

8. Outline • Introduction • Preliminaries & Related Works • Logic Redundancy and Fault Tolerance • Optimization on Fault Masking Rate • Experimental Results • Conclusion

9. Preliminaries & Related Works • Stuck at Faults • Stuck-at-0 / stuck-at-1 • Non-dominating-value stuck-at fault (NDVF) • Dominating-value stuck-at fault (DVF) sa1 untestable= redundant a b b sa0 a b b

10. Preliminaries & Related Works • Dominance and equivalence of stuck-at faults • FIRE [14] • [14] M. Iyer and M. Abramovici. Fire: a fault-independentcombinational redundancy identification algorithm. Very LargeScale Integration (VLSI) Systems, IEEE Transactions on,4(2):295 –301, june 1996.

11. Preliminaries & Related Works • ATPG-based logic rewiring technique • RAR

12. Preliminaries & Related Works • Target wire + alternative wire = A pair of mutually redundant wires • The existence of each of them causes another to be redundant, but both of them cannot be redundant at the same time

13. Preliminaries & Related Works • Fault Masking Rate • A circuit having n wires has a total of 2n potential faults FMR=0 / 11x2 = 0 sa0(a->e) sa0(f->a1) untestable FMR=2 / 2x13 = 0.0769

14. Outline • Introduction • Preliminaries & Related Works • Logic Redundancy and Fault Tolerance • Optimization on Fault Masking Rate • Experimental Results • Conclusion

15. Untestable Faults • Objective: Force the NDVF of both of the target and alternative wires to be untestable • Dominance, Equivalence, FIRE

16. Untestable Faults • sa1(w11) – no alternative wire • sa1(w9) – DVF • sa1(w8) – alternative wire w12 – sa1(w3), sa1(w4) ; w2

17. Redundancy Addition for Yield Enhancement • A coupling fault forest (CFF) • A set of wire faults such that any single fault in the set, regardless of being soft or permanent, is guaranteed to be masked (untestable). The size of a CFF is the number of faults in the set. • If two faults belonging to two different CFFs occur, and do not produce observable faults, each of the two CFFs is said to be an independent CFF.

18. Redundancy Addition for Yield Enhancement • Assume : every fault is an independent event, and its existence will not affect the defect probability of other wires • n wires, m independent CFFs of size k, probability that a wire has stuck-at fault p

19. Redundancy Addition for Yield Enhancement • Adding 10% of redundant wires, yield can be improved by absolute 5.9530%

20. Redundancy Addition for Yield Enhancement

21. Reservation of Untestable Faults • Faults which have previously been made untestable may become testable because of some later redundancy additions • Goal: To maximize the fault masking rate, the chanced of turning untestable faults into testable faults again should be reduced

22. Reservation of Untestable Faults • Untestability assurance function • I = {i1,i2…im} – the set of PIs • F = {f1,f2... fn} – the set of faults • tfi – testability variable - {0,1} • T = {tf1, tf2, … tfn-1} – the set of testability variables • Oi – the i-th POfunction • Oi – the i-th POfunction containing T

23. Reservation of Untestable Faults • Untestability assurance function • Valid conditions for maintaining the circuit function • Considering an untestable fault fi, untestability assurance function: • If afi is 1, fi is untestable; otherwise, it is regarded as testable

24. Reservation of Untestable Faults • Heuristic • Keep implication histories, and then the conditions that lead to the conflicts can be constructed

25. Reservation of Untestable Faults • Heuristic • Case 3

26. Reservation of Untestable Faults Sa0(a→e) untestable Conflict: C(b=0) and C(b=1) C(b=0) : C(b=0) ← tsa1(b→e) (case2) C(b=1) : a=0, e=1 C(b=1) ← C(a=0)tsa1(a → e)C(e=1)tsa0(b → e) C(a=0) ← … … encounter C(a=1) (case1) C(b=1): tsa0(b → e)tsa1(a → e)tsa1(a → f)tsa1(f → a1)tsa1(b → e)tsa1(b → b’)tsa0(b’ → f) Conjunction of C(b=0) C(b=1): tsa0(b → e)tsa1(a → e)tsa1(a → f)tsa1(f → a1)tsa1(b → e)tsa1(b → b’)tsa0(b’ → f) tsa1(b→e)

27. Reservation of Untestable Faults Conjunction of C(b=0) C(b=1): tsa0(b → e)tsa1(a → e)tsa1(a → f)tsa1(f → a1)tsa1(b → e)tsa1(b → b’)tsa0(b’ → f) tsa1(b→e) Addition of e→f makes sa1(a → f) untestable Then sa1(a → f) = 0 Untestibility assurance function is evaluated to 0 -- sa0(a → e) is testable

28. Outline • Introduction • Preliminaries & Related Works • Logic Redundancy and Fault Tolerance • Optimization on Fault Masking Rate • Experimental Results • Conclusion

29. Optimization on Fault Masking Rate Target wires is sorted according to the number of the dominated and equivalent faults of their NDVFs Alternative wires is sorted according to the area overhead The alternative wire is added only if the number of new untestable faults exceeds the number of violated constraints

30. Outline • Introduction • Preliminaries & Related Works • Logic Redundancy and Fault Tolerance • Optimization on Fault Masking Rate • Experimental Results • Conclusion

31. Experimental Results • ISCASand MCNC benchmarks • TSMS 0.18μm standard cell library • C++ • Fault testing - [15] • Limit the area overheadto be around 25% • [15] T. Kirkland and M. R. Mercer. A topological search algorithm for atpg. In DAC ’87: Proceedings of the 24th ACM/IEEE Design Automation Conference, pages 502–508, New York, NY, USA, 1987. ACM.

32. Experimental Results

33. Experimental Results

34. Experimental Results

35. Conclusion • (1) Complement other higher-level fault tolerance techniques to form a hierarchical cross-layer fault tolerance scheme • (2) Avoid the logic intrusion that might be caused by explicit redundancy addition methods • (3) Enhance yield • (4) On average 21.48% of faults can be masked by 25.16% of hardware overhead