Chapter 3. Combinational Logic Design. Combinational Logic. One or more digital signal inputs One or more digital signal outputs Outputs are only functions of current input values (ideal) plus logic propagation delays. I 1. Combinational Logic. O 1. I m. O n. Design Hierarchy.
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Combinational Logic Design
I1
Combinational Logic
O1
Im
On
Technology n. of gates basic units
Vil = 0.8 v
Vol = 0.4v
Noise margin high = 0.4 v
Transition region; neither Hi or Lo!
Noise margin low = 0.4 v
TTL
Logic
Levels
Inverter (NOT operator) has two different forms
Output asserted
active0
Input asserted
active1
Output asserted
active1
Input asserted
active0
X
0
0
1
1
X
F
F
T
T
X
T
T
F
F
Y
0
1
0
1
Y
F
T
F
T
Y
T
F
T
F
X+Y
T
T
T
F
X·Y
0
0
0
1
X·Y
F
F
F
T
Active1
Active0
X
0
0
1
1
X
F
F
T
T
X
T
T
F
F
Y
0
1
0
1
Y
F
T
F
T
Y
T
F
T
F
X+Y
0
1
1
1
X+Y
F
T
T
T
X·Y
T
F
F
F
Active1
Active0
Active0 signal naming and symbol bubbles require some thought to interpret properly
A_L
(active0)
A
(active1)
A
(active1)
A_L
(active0)
Proper active0 signal naming and usage of alternate symbols can clarify the circuit intent
TEMP1
TEMP1_L
TEMP2_L
HEAT
TEMP2
This is really a NOR gate
TEMP1_L
TEMP2_L
HEAT
simplified functions have as many common terms as possible
F1= AB+ CD
F2= CD+C’D’
Here in implementation CD is realized only once
XS3(X) <= BCD(X)
BCD
digit
XS3
digit
b3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
b2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
b1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
b0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
x3
0
0
0
0
0
1
1
1
1
1






x2
0
1
1
1
1
0
0
0
0
1






x1
1
0
0
1
1
0
0
1
1
0






x0
1
0
1
0
1
0
1
0
1
0






Note: Don’t cares
can work to our
advantage during
minimization; we
can assign either
0 or 1 as needed.
zero two
a
fe
Bbc
b
g
AB AB
A =(a0,a1,…..a7), B= (b0,b1,b2….b7)
And F2 such that
F1=1 when A=B
F2=1 when both A=B=0
F1=X0 . X1 … X7
X0
X1
X7
A1=B1
A7=B7
A0=B0