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The George Washington University School of Engineering and Applied Science Department of Electrical and Computer Enginee

The George Washington University School of Engineering and Applied Science Department of Electrical and Computer Engineering. ECE122 Lab 4: VTC & Power Consumption. Jason Woytowich Ritu Bajpai Last modified on September 26, 2007. 5V. Vout. 0V. 0V. 5V. Vin.

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The George Washington University School of Engineering and Applied Science Department of Electrical and Computer Enginee

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  1. The George Washington UniversitySchool of Engineering and Applied ScienceDepartment of Electrical and Computer Engineering ECE122 Lab 4: VTC & Power Consumption Jason Woytowich Ritu Bajpai Last modified on September 26, 2007

  2. 5V Vout 0V 0V 5V Vin Voltage Transfer Characteristic • Vin on the X-Axis and Vout on the Y-Axis

  3. Voltage Transfer Characteristic • A symmetric VTC is one where the Vin vs Vout curve crosses through the dead center of the graph. • Using 5V inputs and outputs this point is 2.5V in and 2.5V out

  4. Lab activity • First we will plot VTC for an inverter. • Check if the VTC is symmetric or not. • If VTC is not symmetric we will find Wp/Wn such that the VTC for an inverter is symmetric.

  5. Step 1: Plotting the VTC • The VTC curve gives us all the output values of the inverter corresponding to all the input values within the range of Gnd and Vdd. • The input varies from 0 (Gnd) to 5V (Vdd) in our case and so does the output.

  6. Replace the pulse input by a DC source in the inverter test circuit.

  7. Select DC transfer sweep analysis and select sweep 1

  8. DC sweep analysis

  9. Choose DC results

  10. Voltage Transfer Characteristic of the inverter

  11. Step 2: Is the VTC symmetric? • The obtained VTC plot is not symmetric. • For symmetric VTC, at intersection of input and output curve, both input and output should be equal to half the maximum possible value.

  12. Step 3: Obtaining symmetric VTC • Keeping the length fixed and the width of NMOS fixed we vary the width of PMOS to obtain a symmetric curve. • That means that we will perform DC sweep that we performed earlier along with the parametric sweep.

  13. Insert command=>analysis=>parametric sweep=>sweep1 Retain the DC sweep command From analysis types choose parametric sweep and sweep for width.

  14. Defining pMOS width as a parameter In the T-Spice code write the following command .param width=35u And in pMOS properties change W=‘28*l’ to W=‘width’ • Thus PMOS width is now defined by parameter width while NMOS width remains unchanged. • The following slide shows the changes incorporated in the T-Spice code.

  15. T-Spice code Command to sweep input voltage: DC SWEEP Parameter initial value set to 35u Command to sweep parameter width from 35u to 100u linearly in steps of 5u: PARAMETRIC SWEEP

  16. Parametric sweep analysis waveform Increasing width Each output plot corresponds to different width, width is varied in the steps of 5u.

  17. Double click on the symmetric VTC to obtain trace characteristics.

  18. Designing for symmetric VTC • Record the width of the pMOS corresponding to symmetric operating point. • In this case width = 80u • In S-Edit substitute this width for the pMOS and perform transient analysis.

  19. Rise time at symmetric operation

  20. Fall time at symmetric operation

  21. Power Consumption • Next we will use Tanner Tools to estimate the power consumption of a design. • We will also identify the sources of power consumption.

  22. Power Consumption • You already have the following test-bench:

  23. Power Consumption • Simulate the circuit over 2 periods with fine resolution (2ns) • Show the waveforms for: • The input and output voltages • The power provided by the power supply • The currents drawn from the power supply and the capacitor

  24. Plotting power output from transient results Identify the name of your voltage source from the T-Spice code.

  25. Plotting current output from transient results Identify the name of your capacitor from the T-Spice code.

  26. Power Consumption10pF Load & 10ns Rise and Fall Times

  27. Power Consumption • Lower the value of the capacitor to 1pF and resimulate

  28. Power Consumption1pF Load & 10ns Rise and Fall Times

  29. Power Consumption • Decrease the rise and fall times of the pulse source to 1ns.

  30. Power Consumption1pF Load & 1ns Rise and Fall Times

  31. Analysis and Results • Report numerical values of your results in tabular form. • Can we vary the width of NMOS instead of PMOS in order to obtain symmetric VTC? If yes, should we increase or decrease it’s value keeping PMOS width fixed? • On the VTC of the inverter show the triode, saturation and cut off region. Which region is used for digital design and which one is used for analog design?

  32. Analysis and Result • Report numerical values of your results in tabular form. • Do you obtain different values of power consumed on varying the load and rise and fall time of the pulse? Compare and analyze your results.

  33. Home work • Draw (on paper) a schematic of a half adder and a full adder (using half adder). Use minimum possible gates. • You will do the schematic design and extract the layout for the above on next turn.

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