1 / 52

CS M51A/EE M16 Winter’05 Section 1 Logic Design of Digital Systems Lecture 15

W’05. CS M51A/EE M16 Winter’05 Section 1 Logic Design of Digital Systems Lecture 15. March 9. Yutao He yutao@cs.ucla.edu 4532B Boelter Hall http://courseweb.seas.ucla.edu/classView.php?term=05W&srs=187154200. Outline. Recap - Combinational macro modules Decoders Encoders Shifters

laith-welch
Download Presentation

CS M51A/EE M16 Winter’05 Section 1 Logic Design of Digital Systems Lecture 15

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. W’05 CS M51A/EE M16 Winter’05 Section 1 Logic Design of Digital SystemsLecture 15 March 9 Yutao He yutao@cs.ucla.edu 4532B Boelter Hall http://courseweb.seas.ucla.edu/classView.php?term=05W&srs=187154200

  2. Outline • Recap - Combinational macro modules • Decoders • Encoders • Shifters • Combinational macro modules • Multiplexers • Demultiplexers • Chapter 11 Sequential Modules • Registers • Shift registers

  3. Combinational Systems Design Analysis Module networks (DEC/ENC, MUX/DEMUX, Shifter.) Chapter 9 Gate networks (AND, OR, NAND, etc.) Chapters 2-6 Chapter 9 - Overview • Basic Questions: • What are each module’s property? • inputs, outputs, functions (high-level and binary level) • How to implement it using logic gates? • How to design a comb. system using these modules? • How to analyze a comb. system using these modules?

  4. E EN x0 0 1 x1 Data Output 2n-Input Multiplexer Data Inputs z x2n-1 2n-1 n-1 0 sn-1 Selection Inputs s0 Multiplexer (MUX)

  5. Multiplexer - Specification High-Level Binary-Level

  6. Multiplexer - Implementation (1) Implementation of MUX with AND/OR gates

  7. Multiplexer - Implementation (2) Implementation of MUX with transmission gates

  8. Multiplexer (Tree) Networks s3 s2 s1 s0 = 1001 s = 9 0 1 1 0 z = x9

  9. Applications of MUXes n-bit Simple Shifter

  10. Applications of MUXes (Cont’d) 4-bit Right-3 Unidirectional Shifter

  11. E EN x0 0 1 x1 2n-Input Multiplexer z x2n-1 2n-1 n-1 0 sn-1 s0 Design Using MUXes • Key observations: • A 2n-Input MUX corresponds to a n-input switching function. • Data outputs store output values of the switching function. • Selection inputs correspond to the inputs of the switching function. • A 2n-Input MUX stores the truth table of a n-input switching function. • Basic Idea: • MUXes are Universal Set • assuming constants 0 and 1 are available

  12. x y carry_in sum carry-out 1-Bit Full Adder x y Cin S Cout 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 Example 9.12 - One-Bit Full Adder • Need two 8-Input MUXes

  13. x y Cin S Cout E = 1 E = 1 0 0 0 0 0 EN EN 0 0 1 1 0 0 0 0 0 0 1 0 1 0 1 1 1 0 0 1 1 0 1 1 0 2 2 Cout 8-Input Multiplexer 1 0 0 1 0 8-Input Multiplexer 3 3 0 1 s 1 0 1 0 1 4 4 1 0 1 1 0 0 1 5 5 0 1 1 1 1 1 1 6 6 0 1 1 1 7 7 0 0 2 1 2 1 x y x y Cin Cin One-Bit Full Adder (Cont’d)

  14. Design Using MUXes with Small Sizes • Is it possible to design a n-input switching function using a 2m-input MUX, where m < n? • The answer is Yes! • How? • Basic idea: • Use data inputs of a MUX to store variables • Basic approaches: • Truth table • K-Map • Boolean algebra

  15. E = 1 EN Cin 0 x y Cin S 1 C’in 4-Input MUX s 0 0 0 0 C’in 2 0 0 1 1 3 Cin 0 1 0 1 1 0 0 1 1 0 1 0 0 1 1 0 1 0 x y 1 1 0 0 1 1 1 1 1-Bit FA Revisited: Using Truth Table • Uses 4-input Muxes Cin C’in C’in Cin

  16. E = 1 x y Cin Cout 0 0 0 0 EN 0 0 0 0 1 0 1 Cin 4-Input MUX 0 1 0 0 Cout Cin 2 0 1 1 1 3 1 1 0 0 0 1 0 1 0 1 1 1 1 0 1 1 1 1 1 x y Using Truth Table (Cont’d) 0 Cin Cin 1

  17. 0 1 1 0 0 1 1 0 E = 1 x EN Cin 0 1 C’in y 4-Input MUX Cin s C’in 2 3 Cin 0 1 3 2 4 5 7 6 1 0 x x y y 1-Bit FA Revisited: Using K-Map Cin C’in C’in Cin

  18. 0 0 0 1 1 0 1 1 x y Cin E = 1 0 1 3 2 4 5 7 6 EN 0 0 1 Cin x 4-Input MUX Cout Cin 2 3 1 y 1 0 x y Using K-Map (Cont’d) 0 Cin Cin 1

  19. E = 1 m0 m1 m2 m3 EN Cin 0 1 C’in 4-Input MUX s C’in 2 3 Cin 1 0 x y 1-Bit FA: Using Boolean Algebra S = x’y’Cin + x’yC’in + xy’C’in + xyCin = (x’y’)Cin + (x’y)C’in + (xy’)C’in + (xy)Cin

  20. m1 m2 m3 E = 1 EN 0 0 1 Cin 4-Input MUX Cout Cin 2 3 1 1 0 x y Using Boolean Algebra (Cont’d) Cout = x’yCin + xy’Cin + xyC’in + xyCin = (x’y)Cin + (xy’)Cin + (xy)(C’in + Cin) = (x’y)Cin + (xy’)Cin + (xy)

  21. E EN z = x0s’+x1s x0 E = 1 0 z 2-Input MUX EN 1 x1 0 1 z 2-Input MUX 0 0 1 E = 1 s 0 EN 0 0 z x 2-Input MUX x1 1 0 x0 Design Using Network of 2-Input MUXes AND gate z = x0 x1 NOT gate z = x’

  22. E EN f(xn-1, …, x1, 0) 0 f(xn-1, …, x1, x0) 2-Input MUX f(xn-1, …, x1, 1) 1 0 x0 Shannon Theorem • The Formula: • f(xn-1, …, x1, x0) = f(xn-1, …, x1, 0) x’0+ f(xn-1, …, x1, 1) x0 • The idea: • A function with more inputs can be decomposed into two functions with fewer inputs. • The Application: • A n-input switching function can be implemented with 2-input MUXes by repeatedly applying the Shannon Theorem.

  23. Example 6.8 • Implement the following function with 2-Input MUXes: • f(x3, x2, x1, x0) = x3( x1+ x2x0) • Decomposition: • The first level: • f(x3, x2, x1, 0) = x3 x1 • f(x3, x2, x1, 1) = x3 (x1 + x2) • The second level: • f(x3, x2, 0, 0) = 0 • f(x3, x2, 0, 1) = x3x2 • f(x3, x2, 1, 0) = x3 • f(x3, x2, 1, 1) = x3

  24. 0 0 0 0 x3 1 f 0 0 0 0 f 0 1 x1 0 x3 1 1 x3 0 0 1 0 0 0 0 x0 x3 x3 1 x1 0 x2 1 x0 0 x2 x1 Example 6.8 (Cont’d) • The third level: • f(x3, 0, 0, 0) = 0, f(x3, 1, 0, 0) = 0 • f(x3, 0, 0, 1) = 0, f(x3, 1, 0, 1) = x3 • f(x3, 0, 1, 0) = x3,f(x3, 1, 1, 0) = x3 • f(x3, 0, 1, 1) = x3,f(x3, 1, 1, 1) = x3

  25. E EN n-1 0 sn-1 Selection Inputs s0 Demultiplexer (DEMUX) y0 0 1 y1 Data Inputs 2n - Output Demultiplexer Data Output x 2n-1 y2n-1

  26. Demultiplexer: High-Level Spec

  27. Example 9.13: 4-Output DEMUX

  28. 4-Output DEMUX (Cont’d)

  29. Application of DEMUXes

  30. Sequential Systems Design Analysis Module networks (Register, Shift Register, Counter) Chapter 11 Flip-Flops (D, JK, SR, T FFs, etc.) Chapters 7-8 Chapter 11 Sequential Modules • Basic Questions: • What are each module’s property? • inputs, outputs, functions (high-level and binary level) • How to implement it using FFs and logic gates? • How to design a sequential system using these modules? • How to analyze a sequential system using these modules?

  31. n-Bit Register

  32. n-Bit Register - High-Level Spec

  33. 4-Bit Register - Implementation

  34. Timing Behavior of Registers

  35. Design Using Registers • Example 11.1

  36. Example 11.1 - Using FFs

  37. LD Y1 y1 2-Bit Register Y0 y0 CLR CLK Example 11.1- Using Register x When x = 1 0

  38. Shift Registers m CLK Shift Register CTL n • Basic Types: • Serial In/Serial Out (SI/SO): m=n=1 • Serial In/Parallel Out (SI/PO): m=1, n> 1 • Parallel In/Serial Out (PI/SO): m>1, n=1 • Parallel In/Parallel Out (PI/PO): m, n > 1

  39. Serial-In/Serial-Out Shift Registers

  40. Serial-In/Parallel-Out Shift Registers

  41. Parallel-In/Serial-Out Shift Registers

  42. Parallel-In/Parallel-Out Shift Registers

  43. PI/PO Shift Registers: High-Level Spec

  44. Present state s(t) = 0101, data input x(t)=1110 PI/PO Shift Register Control

  45. PI/PO Shift Register: Implementation

  46. Applications of Shift Registers • Serial interconnection of two systems

  47. Applications of Shift Registers (Cont’d) • Bit-serial operations

  48. Design Using Shift Registers • For finite-memory sequential systems, shift registers can be used as the state register: • Example 11.2: • z(t) = 1 whenever x(t) • x(t-8) = 1

  49. Design Using Shift Registers (Cont’d) • Shift registers are handy for implementing pattern detectors • Example 11.3 • Design a pattern detector that detects 011101101

  50. Networks of Shift Registers

More Related